Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 201064 [patent_doc_number] => 07640527 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-12-29 [patent_title] => 'Method and apparatus for partial reconfiguration circuit design for a programmable device' [patent_app_type] => utility [patent_app_number] => 11/478208 [patent_app_country] => US [patent_app_date] => 2006-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5193 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/640/07640527.pdf [firstpage_image] =>[orig_patent_app_number] => 11478208 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/478208
Method and apparatus for partial reconfiguration circuit design for a programmable device Jun 28, 2006 Issued
Array ( [id] => 5199209 [patent_doc_number] => 20070298527 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-27 [patent_title] => 'DETERMINING GEOMETRICAL CONFIGURATION OF INTERCONNECT STRUCTURE' [patent_app_type] => utility [patent_app_number] => 11/426053 [patent_app_country] => US [patent_app_date] => 2006-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2645 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0298/20070298527.pdf [firstpage_image] =>[orig_patent_app_number] => 11426053 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/426053
Determining geometrical configuration of interconnect structure Jun 22, 2006 Issued
Array ( [id] => 10518032 [patent_doc_number] => 09245082 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-01-26 [patent_title] => 'High-speed shape-based router' [patent_app_type] => utility [patent_app_number] => 11/425504 [patent_app_country] => US [patent_app_date] => 2006-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 10391 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11425504 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/425504
High-speed shape-based router Jun 20, 2006 Issued
Array ( [id] => 7689772 [patent_doc_number] => 20070234261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Design support device for semiconductor device, design support method for semiconductor device, and design support program for semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/455170 [patent_app_country] => US [patent_app_date] => 2006-06-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 3042 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234261.pdf [firstpage_image] =>[orig_patent_app_number] => 11455170 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/455170
Design support device for semiconductor device, design support method for semiconductor device, and design support program for semiconductor device Jun 18, 2006 Abandoned
Array ( [id] => 9141142 [patent_doc_number] => 08581610 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Method of designing an application specific probe card test system' [patent_app_type] => utility [patent_app_number] => 11/452784 [patent_app_country] => US [patent_app_date] => 2006-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 11551 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 270 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11452784 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/452784
Method of designing an application specific probe card test system Jun 12, 2006 Issued
Array ( [id] => 5167292 [patent_doc_number] => 20070288881 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-13 [patent_title] => 'Method of merging designs of an integrated circuit from a plurality of sources' [patent_app_type] => utility [patent_app_number] => 11/452032 [patent_app_country] => US [patent_app_date] => 2006-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3269 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0288/20070288881.pdf [firstpage_image] =>[orig_patent_app_number] => 11452032 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/452032
Method of merging designs of an integrated circuit from a plurality of sources Jun 11, 2006 Abandoned
Array ( [id] => 261954 [patent_doc_number] => 07574688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-08-11 [patent_title] => 'Using high-level language functions in HDL synthesis tools' [patent_app_type] => utility [patent_app_number] => 11/450222 [patent_app_country] => US [patent_app_date] => 2006-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3730 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/574/07574688.pdf [firstpage_image] =>[orig_patent_app_number] => 11450222 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/450222
Using high-level language functions in HDL synthesis tools Jun 8, 2006 Issued
Array ( [id] => 7589211 [patent_doc_number] => 07665059 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-16 [patent_title] => 'System and method for designing multiple clock domain circuits' [patent_app_type] => utility [patent_app_number] => 11/448582 [patent_app_country] => US [patent_app_date] => 2006-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 7618 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/665/07665059.pdf [firstpage_image] =>[orig_patent_app_number] => 11448582 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448582
System and method for designing multiple clock domain circuits Jun 6, 2006 Issued
Array ( [id] => 5892197 [patent_doc_number] => 20060277518 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'High order synthesizing method and high order synthesizing apparatus' [patent_app_type] => utility [patent_app_number] => 11/447040 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11158 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277518.pdf [firstpage_image] =>[orig_patent_app_number] => 11447040 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/447040
High order synthesizing method and high order synthesizing apparatus Jun 5, 2006 Abandoned
Array ( [id] => 4499606 [patent_doc_number] => 07886249 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-02-08 [patent_title] => 'Printed circuit board design support apparatus, method, and recording medium storing program therefor' [patent_app_type] => utility [patent_app_number] => 11/448960 [patent_app_country] => US [patent_app_date] => 2006-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 28 [patent_no_of_words] => 9441 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/886/07886249.pdf [firstpage_image] =>[orig_patent_app_number] => 11448960 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/448960
Printed circuit board design support apparatus, method, and recording medium storing program therefor Jun 5, 2006 Issued
Array ( [id] => 309757 [patent_doc_number] => 07533357 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-05-12 [patent_title] => 'Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis' [patent_app_type] => utility [patent_app_number] => 11/421863 [patent_app_country] => US [patent_app_date] => 2006-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 5927 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 230 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/533/07533357.pdf [firstpage_image] =>[orig_patent_app_number] => 11421863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/421863
Method and apparatus to target pre-determined spatially varying voltage variation across the area of the VLSI power distribution system using frequency domain analysis Jun 1, 2006 Issued
Array ( [id] => 97132 [patent_doc_number] => 07735035 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-06-08 [patent_title] => 'Method and system for creating a boolean model of multi-path and multi-strength signals for verification' [patent_app_type] => utility [patent_app_number] => 11/444971 [patent_app_country] => US [patent_app_date] => 2006-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 3339 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 21 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/735/07735035.pdf [firstpage_image] =>[orig_patent_app_number] => 11444971 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/444971
Method and system for creating a boolean model of multi-path and multi-strength signals for verification May 30, 2006 Issued
Array ( [id] => 5627169 [patent_doc_number] => 20060265674 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-23 [patent_title] => 'System and method for statistical design rule checking' [patent_app_type] => utility [patent_app_number] => 11/437600 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5190 [patent_no_of_claims] => 35 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0265/20060265674.pdf [firstpage_image] =>[orig_patent_app_number] => 11437600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437600
System and method for statistical design rule checking May 18, 2006 Issued
Array ( [id] => 5143898 [patent_doc_number] => 20070006114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Method and system for incorporation of patterns and design rule checking' [patent_app_type] => utility [patent_app_number] => 11/437320 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4740 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006114.pdf [firstpage_image] =>[orig_patent_app_number] => 11437320 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/437320
Method and system for incorporation of patterns and design rule checking May 18, 2006 Issued
Array ( [id] => 9119 [patent_doc_number] => 07818706 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 11/436640 [patent_app_country] => US [patent_app_date] => 2006-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3883 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/818/07818706.pdf [firstpage_image] =>[orig_patent_app_number] => 11436640 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/436640
Semiconductor integrated circuit device May 18, 2006 Issued
Array ( [id] => 5030087 [patent_doc_number] => 20070271534 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-22 [patent_title] => 'Trace Equivalence Identification Through Structural Isomorphism Detection With On The Fly Logic Writing' [patent_app_type] => utility [patent_app_number] => 11/383770 [patent_app_country] => US [patent_app_date] => 2006-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2810 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0271/20070271534.pdf [firstpage_image] =>[orig_patent_app_number] => 11383770 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/383770
Trace equivalence identification through structural isomorphism detection with on the fly logic writing May 16, 2006 Issued
Array ( [id] => 8355155 [patent_doc_number] => 08250500 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-21 [patent_title] => 'Method and apparatus for deriving signal activities for power analysis and optimization' [patent_app_type] => utility [patent_app_number] => 11/414803 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8901 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11414803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414803
Method and apparatus for deriving signal activities for power analysis and optimization Apr 30, 2006 Issued
Array ( [id] => 10873382 [patent_doc_number] => 08898603 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2014-11-25 [patent_title] => 'Method and apparatus for deriving signal activities for power analysis and optimization' [patent_app_type] => utility [patent_app_number] => 11/414933 [patent_app_country] => US [patent_app_date] => 2006-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8852 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11414933 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/414933
Method and apparatus for deriving signal activities for power analysis and optimization Apr 30, 2006 Issued
Array ( [id] => 5226770 [patent_doc_number] => 20070256037 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-11-01 [patent_title] => 'Net-list organization tools' [patent_app_type] => utility [patent_app_number] => 11/411593 [patent_app_country] => US [patent_app_date] => 2006-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8483 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0256/20070256037.pdf [firstpage_image] =>[orig_patent_app_number] => 11411593 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/411593
Net-list organization tools Apr 25, 2006 Abandoned
Array ( [id] => 79769 [patent_doc_number] => 07752594 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system' [patent_app_type] => utility [patent_app_number] => 11/409273 [patent_app_country] => US [patent_app_date] => 2006-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 12617 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/752/07752594.pdf [firstpage_image] =>[orig_patent_app_number] => 11409273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/409273
Semiconductor failure analysis apparatus, failure analysis method, failure analysis program, and failure analysis system Apr 23, 2006 Issued
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