Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8120407 [patent_doc_number] => 08161425 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-04-17 [patent_title] => 'Method and system for implementing timing aware metal fill' [patent_app_type] => utility [patent_app_number] => 11/407873 [patent_app_country] => US [patent_app_date] => 2006-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6812 [patent_no_of_claims] => 54 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/161/08161425.pdf [firstpage_image] =>[orig_patent_app_number] => 11407873 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/407873
Method and system for implementing timing aware metal fill Apr 18, 2006 Issued
Array ( [id] => 5892219 [patent_doc_number] => 20060277521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-12-07 [patent_title] => 'Method, program product and apparatus for performing double exposure lithography' [patent_app_type] => utility [patent_app_number] => 11/402273 [patent_app_country] => US [patent_app_date] => 2006-04-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7143 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0277/20060277521.pdf [firstpage_image] =>[orig_patent_app_number] => 11402273 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/402273
Method, program product and apparatus for performing double exposure lithography Apr 11, 2006 Issued
Array ( [id] => 4592926 [patent_doc_number] => 07853902 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-12-14 [patent_title] => 'Method for designing a circuit, particularly having an active component' [patent_app_type] => utility [patent_app_number] => 11/401351 [patent_app_country] => US [patent_app_date] => 2006-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 12847 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 242 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/853/07853902.pdf [firstpage_image] =>[orig_patent_app_number] => 11401351 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/401351
Method for designing a circuit, particularly having an active component Apr 10, 2006 Issued
Array ( [id] => 27590 [patent_doc_number] => 07802218 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-09-21 [patent_title] => 'Layout analysis method and apparatus for semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/396660 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 3174 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 220 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802218.pdf [firstpage_image] =>[orig_patent_app_number] => 11396660 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/396660
Layout analysis method and apparatus for semiconductor integrated circuit Apr 3, 2006 Issued
Array ( [id] => 5255249 [patent_doc_number] => 20070136705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-06-14 [patent_title] => 'Timing analysis method and device' [patent_app_type] => utility [patent_app_number] => 11/396540 [patent_app_country] => US [patent_app_date] => 2006-04-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5450 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0136/20070136705.pdf [firstpage_image] =>[orig_patent_app_number] => 11396540 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/396540
Timing analysis method and device Apr 3, 2006 Abandoned
Array ( [id] => 5755873 [patent_doc_number] => 20060225022 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-05 [patent_title] => 'Method, apparatus and program for determining the relationship of correspondence between register transfer level description and behavioral description' [patent_app_type] => utility [patent_app_number] => 11/395210 [patent_app_country] => US [patent_app_date] => 2006-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 5422 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20060225022.pdf [firstpage_image] =>[orig_patent_app_number] => 11395210 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/395210
Method, apparatus and program for determining the relationship of correspondence between register transfer level description and behavioral description Apr 2, 2006 Abandoned
Array ( [id] => 4582462 [patent_doc_number] => 07840913 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-11-23 [patent_title] => 'Restricting state diagrams with a set of predefined requirements to restrict a state diagram to a state diagram of a moore or mealy machine' [patent_app_type] => utility [patent_app_number] => 11/394574 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7541 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/840/07840913.pdf [firstpage_image] =>[orig_patent_app_number] => 11394574 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394574
Restricting state diagrams with a set of predefined requirements to restrict a state diagram to a state diagram of a moore or mealy machine Mar 30, 2006 Issued
Array ( [id] => 79736 [patent_doc_number] => 07752576 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-07-06 [patent_title] => 'Design support apparatus, design support method, and computer product for designing function module from specification description' [patent_app_type] => utility [patent_app_number] => 11/394390 [patent_app_country] => US [patent_app_date] => 2006-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 21 [patent_no_of_words] => 7486 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 226 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/752/07752576.pdf [firstpage_image] =>[orig_patent_app_number] => 11394390 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/394390
Design support apparatus, design support method, and computer product for designing function module from specification description Mar 30, 2006 Issued
Array ( [id] => 5861760 [patent_doc_number] => 20060230374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-10-12 [patent_title] => 'System and method for analyzing crosstalk occurring in a semiconductor integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/393074 [patent_app_country] => US [patent_app_date] => 2006-03-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 9332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0230/20060230374.pdf [firstpage_image] =>[orig_patent_app_number] => 11393074 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/393074
System and method for analyzing crosstalk occurring in a semiconductor integrated circuit Mar 29, 2006 Issued
Array ( [id] => 7689780 [patent_doc_number] => 20070234253 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-10-04 [patent_title] => 'Multiple mode approach to building static timing models for digital transistor circuits' [patent_app_type] => utility [patent_app_number] => 11/391880 [patent_app_country] => US [patent_app_date] => 2006-03-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6259 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0234/20070234253.pdf [firstpage_image] =>[orig_patent_app_number] => 11391880 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/391880
Multiple mode approach to building static timing models for digital transistor circuits Mar 28, 2006 Abandoned
Array ( [id] => 5734761 [patent_doc_number] => 20060259878 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-16 [patent_title] => 'Automated processor generation system for designing a configurable processor and method for the same' [patent_app_type] => utility [patent_app_number] => 11/391773 [patent_app_country] => US [patent_app_date] => 2006-03-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 15 [patent_no_of_words] => 22700 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0259/20060259878.pdf [firstpage_image] =>[orig_patent_app_number] => 11391773 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/391773
Automated processor generation system for designing a configurable processor and method for the same Mar 26, 2006 Issued
Array ( [id] => 398036 [patent_doc_number] => 07302656 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2007-11-27 [patent_title] => 'Method and system for performing functional verification of logic circuits' [patent_app_type] => utility [patent_app_number] => 11/385928 [patent_app_country] => US [patent_app_date] => 2006-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4611 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/302/07302656.pdf [firstpage_image] =>[orig_patent_app_number] => 11385928 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/385928
Method and system for performing functional verification of logic circuits Mar 20, 2006 Issued
Array ( [id] => 336980 [patent_doc_number] => 07509609 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-03-24 [patent_title] => 'Methods and apparatus for reducing timing skew' [patent_app_type] => utility [patent_app_number] => 11/376600 [patent_app_country] => US [patent_app_date] => 2006-03-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5605 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 285 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/509/07509609.pdf [firstpage_image] =>[orig_patent_app_number] => 11376600 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/376600
Methods and apparatus for reducing timing skew Mar 14, 2006 Issued
Array ( [id] => 856485 [patent_doc_number] => 07380225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-05-27 [patent_title] => 'Method and computer program for efficient cell failure rate estimation in cell arrays' [patent_app_type] => utility [patent_app_number] => 11/375477 [patent_app_country] => US [patent_app_date] => 2006-03-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4189 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/380/07380225.pdf [firstpage_image] =>[orig_patent_app_number] => 11375477 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/375477
Method and computer program for efficient cell failure rate estimation in cell arrays Mar 13, 2006 Issued
Array ( [id] => 137342 [patent_doc_number] => 07698661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-04-13 [patent_title] => 'Circuit automatic generation apparatus and method' [patent_app_type] => utility [patent_app_number] => 11/370010 [patent_app_country] => US [patent_app_date] => 2006-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 15303 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 395 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/698/07698661.pdf [firstpage_image] =>[orig_patent_app_number] => 11370010 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/370010
Circuit automatic generation apparatus and method Mar 7, 2006 Issued
Array ( [id] => 5006682 [patent_doc_number] => 20070204255 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-08-30 [patent_title] => 'Net routing' [patent_app_type] => utility [patent_app_number] => 11/364382 [patent_app_country] => US [patent_app_date] => 2006-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7934 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0204/20070204255.pdf [firstpage_image] =>[orig_patent_app_number] => 11364382 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/364382
Net routing Feb 27, 2006 Abandoned
Array ( [id] => 5789339 [patent_doc_number] => 20060206853 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Method of producing mask inspection data, method of manufacturing a photo mask and method of manufacturing a semiconductor device' [patent_app_type] => utility [patent_app_number] => 11/360688 [patent_app_country] => US [patent_app_date] => 2006-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3242 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0206/20060206853.pdf [firstpage_image] =>[orig_patent_app_number] => 11360688 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/360688
Method of producing mask inspection data, method of manufacturing a photo mask and method of manufacturing a semiconductor device Feb 23, 2006 Abandoned
Array ( [id] => 4590536 [patent_doc_number] => 07831948 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-11-09 [patent_title] => 'Method and system for automatically generating schematics' [patent_app_type] => utility [patent_app_number] => 11/346103 [patent_app_country] => US [patent_app_date] => 2006-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3846 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/831/07831948.pdf [firstpage_image] =>[orig_patent_app_number] => 11346103 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/346103
Method and system for automatically generating schematics Feb 1, 2006 Issued
Array ( [id] => 810195 [patent_doc_number] => 07421675 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-09-02 [patent_title] => 'Annotating timing information for a circuit design for increased timing accuracy' [patent_app_type] => utility [patent_app_number] => 11/333863 [patent_app_country] => US [patent_app_date] => 2006-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 7 [patent_no_of_words] => 3958 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 141 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421675.pdf [firstpage_image] =>[orig_patent_app_number] => 11333863 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/333863
Annotating timing information for a circuit design for increased timing accuracy Jan 16, 2006 Issued
Array ( [id] => 462737 [patent_doc_number] => 07246334 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-07-17 [patent_title] => 'Topological analysis based method for identifying state nodes in a sequential digital circuit at the transistor level' [patent_app_type] => utility [patent_app_number] => 11/305253 [patent_app_country] => US [patent_app_date] => 2005-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 4871 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 343 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/246/07246334.pdf [firstpage_image] =>[orig_patent_app_number] => 11305253 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/305253
Topological analysis based method for identifying state nodes in a sequential digital circuit at the transistor level Dec 15, 2005 Issued
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