Anne Marie Sabrina Wehbe

Array ( [id] => 5917060 [patent_doc_number] => 20060129967 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-15 [patent_title] => 'System, method and program for generating mask data, exposure mask and semiconductor device in consideration of optical proximity effects' [patent_app_type] => utility [patent_app_number] => 11/298840 [patent_app_country] => US [patent_app_date] => 2005-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12058 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0129/20060129967.pdf [firstpage_image] =>[orig_patent_app_number] => 11298840 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 156365 [patent_doc_number] => 07681168 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-03-16 [patent_title] => 'Semiconductor integrated device, method of designing semiconductor integrated device, device for designing the same, and program' [patent_app_type] => utility [patent_app_number] => 11/290533 [patent_app_country] => US [patent_app_date] => 2005-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 22 [patent_no_of_words] => 6270 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/681/07681168.pdf [firstpage_image] =>[orig_patent_app_number] => 11290533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5615353 [patent_doc_number] => 20060117283 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-01 [patent_title] => 'Integrated circuit verification method, verification apparatus, and verification program' [patent_app_type] => utility [patent_app_number] => 11/283693 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3593 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0117/20060117283.pdf [firstpage_image] =>[orig_patent_app_number] => 11283693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5847405 [patent_doc_number] => 20060123381 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-06-08 [patent_title] => 'Data generating system, patterning data generating apparatus, method of generating patterning data and storage medium carrying patterning data' [patent_app_type] => utility [patent_app_number] => 11/283973 [patent_app_country] => US [patent_app_date] => 2005-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12391 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0123/20060123381.pdf [firstpage_image] =>[orig_patent_app_number] => 11283973 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5096730 [patent_doc_number] => 20070118339 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-05-24 [patent_title] => 'Method and apparatus for distinguishing combinational designs' [patent_app_type] => utility [patent_app_number] => 11/282883 [patent_app_country] => US [patent_app_date] => 2005-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 34 [patent_figures_cnt] => 34 [patent_no_of_words] => 14115 [patent_no_of_claims] => 51 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0118/20070118339.pdf [firstpage_image] =>[orig_patent_app_number] => 11282883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5778606 [patent_doc_number] => 20060107246 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-18 [patent_title] => 'Designing method for high-frequency transistor and high-frequency transistor having multi-finger gate' [patent_app_type] => utility [patent_app_number] => 11/267993 [patent_app_country] => US [patent_app_date] => 2005-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 17353 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0107/20060107246.pdf [firstpage_image] =>[orig_patent_app_number] => 11267993 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 27599 [patent_doc_number] => 07802221 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-09-21 [patent_title] => 'Design tool with graphical interconnect matrix' [patent_app_type] => utility [patent_app_number] => 11/266074 [patent_app_country] => US [patent_app_date] => 2005-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8769 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 224 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/802/07802221.pdf [firstpage_image] =>[orig_patent_app_number] => 11266074 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5807607 [patent_doc_number] => 20060093961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-04 [patent_title] => 'Method of verifying electron beam data' [patent_app_type] => utility [patent_app_number] => 11/262710 [patent_app_country] => US [patent_app_date] => 2005-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3352 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20060093961.pdf [firstpage_image] =>[orig_patent_app_number] => 11262710 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173704 [patent_doc_number] => 20070074144 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Method and system for selective optical pattern compensation' [patent_app_type] => utility [patent_app_number] => 11/261455 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5412 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074144.pdf [firstpage_image] =>[orig_patent_app_number] => 11261455 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5143888 [patent_doc_number] => 20070006104 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-01-04 [patent_title] => 'Electronic-circuit analysis program, method, and apparatus' [patent_app_type] => utility [patent_app_number] => 11/259273 [patent_app_country] => US [patent_app_date] => 2005-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 8037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0006/20070006104.pdf [firstpage_image] =>[orig_patent_app_number] => 11259273 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 87952 [patent_doc_number] => 07743349 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-06-22 [patent_title] => 'Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit' [patent_app_type] => utility [patent_app_number] => 11/254643 [patent_app_country] => US [patent_app_date] => 2005-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 10468 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/743/07743349.pdf [firstpage_image] =>[orig_patent_app_number] => 11254643 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5137637 [patent_doc_number] => 20070079266 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-04-05 [patent_title] => 'Method and computer program for analysis of an integrated circuit design to identify and resolve a problematic structure characterized by multiple rule violations using a design closure knowledge base and a physical design database' [patent_app_type] => utility [patent_app_number] => 11/241033 [patent_app_country] => US [patent_app_date] => 2005-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5258 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0079/20070079266.pdf [firstpage_image] =>[orig_patent_app_number] => 11241033 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 810187 [patent_doc_number] => 07421669 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-09-02 [patent_title] => 'Using constraints in design verification' [patent_app_type] => utility [patent_app_number] => 11/236451 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4074 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/421/07421669.pdf [firstpage_image] =>[orig_patent_app_number] => 11236451 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5173702 [patent_doc_number] => 20070074142 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-29 [patent_title] => 'Integrated circuit layout methods' [patent_app_type] => utility [patent_app_number] => 11/235964 [patent_app_country] => US [patent_app_date] => 2005-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6509 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20070074142.pdf [firstpage_image] =>[orig_patent_app_number] => 11235964 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 321671 [patent_doc_number] => 07523434 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-04-21 [patent_title] => 'Interfacing with a dynamically configurable arithmetic unit' [patent_app_type] => utility [patent_app_number] => 11/234490 [patent_app_country] => US [patent_app_date] => 2005-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7730 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/523/07523434.pdf [firstpage_image] =>[orig_patent_app_number] => 11234490 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4684148 [patent_doc_number] => 20080250374 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-10-09 [patent_title] => 'Method of Making an Integrated Circuit' [patent_app_type] => utility [patent_app_number] => 12/067583 [patent_app_country] => US [patent_app_date] => 2005-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4201 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0250/20080250374.pdf [firstpage_image] =>[orig_patent_app_number] => 12067583 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 5058843 [patent_doc_number] => 20070061765 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-03-15 [patent_title] => 'Method and system for case-splitting on nodes in a symbolic simulation framework' [patent_app_type] => utility [patent_app_number] => 11/225651 [patent_app_country] => US [patent_app_date] => 2005-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5140 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0061/20070061765.pdf [firstpage_image] =>[orig_patent_app_number] => 11225651 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4577963 [patent_doc_number] => 07823095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and system for implementing parallel processing of electronic design automation tools' [patent_app_type] => utility [patent_app_number] => 11/225853 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5816 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823095.pdf [firstpage_image] =>[orig_patent_app_number] => 11225853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4577963 [patent_doc_number] => 07823095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and system for implementing parallel processing of electronic design automation tools' [patent_app_type] => utility [patent_app_number] => 11/225853 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5816 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823095.pdf [firstpage_image] =>[orig_patent_app_number] => 11225853 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4577963 [patent_doc_number] => 07823095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and system for implementing parallel processing of electronic design automation tools' [patent_app_type] => utility [patent_app_number] => 11/225853 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5816 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823095.pdf [firstpage_image] =>[orig_patent_app_number] => 11225853 [rel_patent_id] =>[rel_patent_doc_number] =>)