Search

Anne Marie Sabrina Wehbe

Examiner (ID: 9163, Phone: (571)272-0737 , Office: P/1633 )

Most Active Art Unit
1633
Art Unit(s)
1632, 1634, 1633
Total Applications
1343
Issued Applications
603
Pending Applications
241
Abandoned Applications
542

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4577963 [patent_doc_number] => 07823095 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2010-10-26 [patent_title] => 'Method and system for implementing parallel processing of electronic design automation tools' [patent_app_type] => utility [patent_app_number] => 11/225853 [patent_app_country] => US [patent_app_date] => 2005-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 5816 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/823/07823095.pdf [firstpage_image] =>[orig_patent_app_number] => 11225853 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/225853
Method and system for implementing parallel processing of electronic design automation tools Sep 11, 2005 Issued
Array ( [id] => 4488905 [patent_doc_number] => 07908572 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-15 [patent_title] => 'Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity' [patent_app_type] => utility [patent_app_number] => 11/221533 [patent_app_country] => US [patent_app_date] => 2005-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6691 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/908/07908572.pdf [firstpage_image] =>[orig_patent_app_number] => 11221533 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/221533
Creating and applying variable bias rules in rule-based optical proximity correction for reduced complexity Sep 7, 2005 Issued
Array ( [id] => 877947 [patent_doc_number] => 07363606 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-04-22 [patent_title] => 'Flip-flop insertion method for global interconnect pipelining' [patent_app_type] => utility [patent_app_number] => 11/211003 [patent_app_country] => US [patent_app_date] => 2005-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 14 [patent_no_of_words] => 6620 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/363/07363606.pdf [firstpage_image] =>[orig_patent_app_number] => 11211003 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/211003
Flip-flop insertion method for global interconnect pipelining Aug 22, 2005 Issued
Array ( [id] => 5774470 [patent_doc_number] => 20050268261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-12-01 [patent_title] => 'Circuit analyzing method and circuit analyzing device' [patent_app_type] => utility [patent_app_number] => 11/136663 [patent_app_country] => US [patent_app_date] => 2005-05-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8102 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0268/20050268261.pdf [firstpage_image] =>[orig_patent_app_number] => 11136663 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/136663
Circuit analyzing method and circuit analyzing device May 24, 2005 Abandoned
Array ( [id] => 882644 [patent_doc_number] => 07360178 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-04-15 [patent_title] => 'Mixed-signal functions using R-cells' [patent_app_type] => utility [patent_app_number] => 11/136180 [patent_app_country] => US [patent_app_date] => 2005-05-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5419 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/360/07360178.pdf [firstpage_image] =>[orig_patent_app_number] => 11136180 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/136180
Mixed-signal functions using R-cells May 23, 2005 Issued
Array ( [id] => 5663217 [patent_doc_number] => 20060253813 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-11-09 [patent_title] => 'Design rule violations check (DRC) of IC\'s (integrated circuits) mask layout database, via the internet method and computer software' [patent_app_type] => utility [patent_app_number] => 11/120262 [patent_app_country] => US [patent_app_date] => 2005-05-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0253/20060253813.pdf [firstpage_image] =>[orig_patent_app_number] => 11120262 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/120262
Design rule violations check (DRC) of IC's (integrated circuits) mask layout database, via the internet method and computer software May 2, 2005 Abandoned
Array ( [id] => 922302 [patent_doc_number] => 07325223 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-01-29 [patent_title] => 'Modification of pixelated photolithography masks based on electric fields' [patent_app_type] => utility [patent_app_number] => 11/096613 [patent_app_country] => US [patent_app_date] => 2005-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 3929 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/325/07325223.pdf [firstpage_image] =>[orig_patent_app_number] => 11096613 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/096613
Modification of pixelated photolithography masks based on electric fields Mar 30, 2005 Issued
Array ( [id] => 4616669 [patent_doc_number] => 07992122 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'Method of placing and routing for power optimization and timing closure' [patent_app_type] => utility [patent_app_number] => 11/093713 [patent_app_country] => US [patent_app_date] => 2005-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6396 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/992/07992122.pdf [firstpage_image] =>[orig_patent_app_number] => 11093713 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/093713
Method of placing and routing for power optimization and timing closure Mar 24, 2005 Issued
Array ( [id] => 908882 [patent_doc_number] => 07337424 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-02-26 [patent_title] => 'Flexible shape identification for optical proximity correction in semiconductor fabrication' [patent_app_type] => utility [patent_app_number] => 11/089723 [patent_app_country] => US [patent_app_date] => 2005-03-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 3944 [patent_no_of_claims] => 40 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/337/07337424.pdf [firstpage_image] =>[orig_patent_app_number] => 11089723 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/089723
Flexible shape identification for optical proximity correction in semiconductor fabrication Mar 23, 2005 Issued
Array ( [id] => 5782366 [patent_doc_number] => 20060203581 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-09-14 [patent_title] => 'Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions' [patent_app_type] => utility [patent_app_number] => 11/077313 [patent_app_country] => US [patent_app_date] => 2005-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 3455 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0203/20060203581.pdf [firstpage_image] =>[orig_patent_app_number] => 11077313 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/077313
Efficient method and computer program for modeling and improving static memory performance across process variations and environmental conditions Mar 9, 2005 Abandoned
Array ( [id] => 5012593 [patent_doc_number] => 20070283072 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-12-06 [patent_title] => 'Method And Apparatus For Generating Configuration Data' [patent_app_type] => utility [patent_app_number] => 10/590583 [patent_app_country] => US [patent_app_date] => 2005-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14311 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0283/20070283072.pdf [firstpage_image] =>[orig_patent_app_number] => 10590583 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/590583
Method And Apparatus For Generating Configuration Data Feb 24, 2005 Abandoned
Array ( [id] => 396950 [patent_doc_number] => 07299430 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2007-11-20 [patent_title] => 'Reducing design execution run time bit stream size for device testing' [patent_app_type] => utility [patent_app_number] => 11/064369 [patent_app_country] => US [patent_app_date] => 2005-02-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4862 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/299/07299430.pdf [firstpage_image] =>[orig_patent_app_number] => 11064369 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/064369
Reducing design execution run time bit stream size for device testing Feb 22, 2005 Issued
Array ( [id] => 864548 [patent_doc_number] => 07373621 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2008-05-13 [patent_title] => 'Constraint-driven test generation for programmable logic device integrated circuits' [patent_app_type] => utility [patent_app_number] => 11/048356 [patent_app_country] => US [patent_app_date] => 2005-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 20 [patent_no_of_words] => 10139 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/373/07373621.pdf [firstpage_image] =>[orig_patent_app_number] => 11048356 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/048356
Constraint-driven test generation for programmable logic device integrated circuits Jan 31, 2005 Issued
Array ( [id] => 7262671 [patent_doc_number] => 20050144583 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-06-30 [patent_title] => 'Method and data-processing system for rule-based optical proximity correction with simulataneous scatter bar insertion' [patent_app_type] => utility [patent_app_number] => 11/032483 [patent_app_country] => US [patent_app_date] => 2005-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5172 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20050144583.pdf [firstpage_image] =>[orig_patent_app_number] => 11032483 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/032483
Method and data-processing system for rule-based optical proximity correction with simulataneous scatter bar insertion Jan 9, 2005 Abandoned
Array ( [id] => 245219 [patent_doc_number] => 07590963 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-15 [patent_title] => 'Integrating multiple electronic design applications' [patent_app_type] => utility [patent_app_number] => 10/983132 [patent_app_country] => US [patent_app_date] => 2004-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 5353 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 415 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/590/07590963.pdf [firstpage_image] =>[orig_patent_app_number] => 10983132 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/983132
Integrating multiple electronic design applications Nov 7, 2004 Issued
Array ( [id] => 5867236 [patent_doc_number] => 20060101368 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-05-11 [patent_title] => 'Distributed electronic design automation environment' [patent_app_type] => utility [patent_app_number] => 10/960793 [patent_app_country] => US [patent_app_date] => 2004-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 70 [patent_no_of_words] => 25841 [patent_no_of_claims] => 47 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0101/20060101368.pdf [firstpage_image] =>[orig_patent_app_number] => 10960793 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/960793
Distributed electronic design automation environment Oct 7, 2004 Abandoned
Array ( [id] => 5816224 [patent_doc_number] => 20060085373 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-20 [patent_title] => 'Method and apparatus for creating relationships over a network' [patent_app_type] => utility [patent_app_number] => 10/956489 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 6330 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20060085373.pdf [firstpage_image] =>[orig_patent_app_number] => 10956489 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956489
Method and apparatus for creating relationships over a network Sep 29, 2004 Abandoned
Array ( [id] => 5722128 [patent_doc_number] => 20060074904 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2006-04-06 [patent_title] => 'Content delivery rendering engine' [patent_app_type] => utility [patent_app_number] => 10/956999 [patent_app_country] => US [patent_app_date] => 2004-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5153 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0074/20060074904.pdf [firstpage_image] =>[orig_patent_app_number] => 10956999 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/956999
Content delivery rendering engine Sep 29, 2004 Abandoned
Array ( [id] => 6917954 [patent_doc_number] => 20050095515 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2005-05-05 [patent_title] => 'Methods and systems for processing overlay data' [patent_app_type] => utility [patent_app_number] => 10/928053 [patent_app_country] => US [patent_app_date] => 2004-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7344 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0095/20050095515.pdf [firstpage_image] =>[orig_patent_app_number] => 10928053 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/928053
Methods and systems for processing overlay data Aug 26, 2004 Abandoned
Array ( [id] => 4990792 [patent_doc_number] => 20070157133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2007-07-05 [patent_title] => 'Circuit network analysis using algebraic multigrid approach' [patent_app_type] => utility [patent_app_number] => 10/558842 [patent_app_country] => US [patent_app_date] => 2004-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6323 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0157/20070157133.pdf [firstpage_image] =>[orig_patent_app_number] => 10558842 [rel_patent_id] =>[rel_patent_doc_number] =>)
10/558842
Circuit network analysis using algebraic multigrid approach May 31, 2004 Issued
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