Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 11220793 [patent_doc_number] => 09449132 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'Configuring a programmable device using high-level language' [patent_app_type] => utility [patent_app_number] => 14/590367 [patent_app_country] => US [patent_app_date] => 2015-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 5984 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14590367 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/590367
Configuring a programmable device using high-level language Jan 5, 2015 Issued
Array ( [id] => 11252295 [patent_doc_number] => 09477799 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-10-25 [patent_title] => 'Hierarchical determination of metrics for component-based parameterized SoCs' [patent_app_type] => utility [patent_app_number] => 14/554813 [patent_app_country] => US [patent_app_date] => 2014-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 12091 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 127 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14554813 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/554813
Hierarchical determination of metrics for component-based parameterized SoCs Nov 25, 2014 Issued
Array ( [id] => 10962953 [patent_doc_number] => 20140365983 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'INTEGRATION OF LITHOGRAPHY APPARATUS AND MASK OPTIMIZATION PROCESS WITH MULTIPLE PATTERNING PROCESS' [patent_app_type] => utility [patent_app_number] => 14/468635 [patent_app_country] => US [patent_app_date] => 2014-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11001 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14468635 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/468635
Integration of lithography apparatus and mask optimization process with multiple patterning process Aug 25, 2014 Issued
Array ( [id] => 10962952 [patent_doc_number] => 20140365982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-12-11 [patent_title] => 'Method for Making a Mask With a Phase Bar in An Integrated Circuit Design Layout' [patent_app_type] => utility [patent_app_number] => 14/465449 [patent_app_country] => US [patent_app_date] => 2014-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4449 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14465449 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/465449
Method for making a mask with a phase bar in an integrated circuit design layout Aug 20, 2014 Issued
Array ( [id] => 10610180 [patent_doc_number] => 09330216 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-05-03 [patent_title] => 'Integrated circuit design synthesis using slack diagrams' [patent_app_type] => utility [patent_app_number] => 14/320589 [patent_app_country] => US [patent_app_date] => 2014-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4253 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14320589 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/320589
Integrated circuit design synthesis using slack diagrams Jun 29, 2014 Issued
Array ( [id] => 10417123 [patent_doc_number] => 20150302133 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-10-22 [patent_title] => 'SYSTEMS AND METHODS FOR AUTOMATED FUNCTIONAL COVERAGE GENERATION AND MANAGEMENT FOR IC DESIGN PROTOCOLS' [patent_app_type] => utility [patent_app_number] => 14/288121 [patent_app_country] => US [patent_app_date] => 2014-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5763 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14288121 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/288121
System and method for automated functional coverage generation and management for IC design protocols May 26, 2014 Issued
Array ( [id] => 11207160 [patent_doc_number] => 09436787 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Method of fabricating an integrated circuit with optimized pattern density uniformity' [patent_app_type] => utility [patent_app_number] => 14/252464 [patent_app_country] => US [patent_app_date] => 2014-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5807 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14252464 [rel_patent_id] =>[rel_patent_doc_number] =>)
14/252464
Method of fabricating an integrated circuit with optimized pattern density uniformity Apr 13, 2014 Issued
Array ( [id] => 9424379 [patent_doc_number] => 20140109030 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-04-17 [patent_title] => 'Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria' [patent_app_type] => utility [patent_app_number] => 13/956220 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956220 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956220
Method of Determining Electromigration (EM) Lifetimes and Lifetime Criteria Jul 30, 2013 Abandoned
Array ( [id] => 11214012 [patent_doc_number] => 09443050 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Low-voltage swing circuit modifications' [patent_app_type] => utility [patent_app_number] => 13/956140 [patent_app_country] => US [patent_app_date] => 2013-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 10734 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13956140 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/956140
Low-voltage swing circuit modifications Jul 30, 2013 Issued
Array ( [id] => 9283193 [patent_doc_number] => 20140033161 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'ACCURATE APPROXIMATION OF THE OBJECTIVE FUNCTION FOR SOLVING THE GATE-SIZING PROBLEM USING A NUMERICAL SOLVER' [patent_app_type] => utility [patent_app_number] => 13/954922 [patent_app_country] => US [patent_app_date] => 2013-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 8049 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13954922 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/954922
Accurate approximation of the objective function for solving the gate-sizing problem using a numerical solver Jul 29, 2013 Issued
Array ( [id] => 9513462 [patent_doc_number] => 20140149954 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-05-29 [patent_title] => 'STRESS EFFECT MODEL OPTIMIZATION IN INTEGRATED CIRCUIT SPICE MODEL' [patent_app_type] => utility [patent_app_number] => 13/943670 [patent_app_country] => US [patent_app_date] => 2013-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 4811 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13943670 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/943670
STRESS EFFECT MODEL OPTIMIZATION IN INTEGRATED CIRCUIT SPICE MODEL Jul 15, 2013 Abandoned
Array ( [id] => 9386401 [patent_doc_number] => 20140089884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-03-27 [patent_title] => 'DESIGN SUPPORT METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/939630 [patent_app_country] => US [patent_app_date] => 2013-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 31 [patent_no_of_words] => 8240 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13939630 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/939630
DESIGN SUPPORT METHOD AND APPARATUS Jul 10, 2013 Abandoned
Array ( [id] => 9683114 [patent_doc_number] => 20140239877 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-08-28 [patent_title] => 'TWO-WAY DIRECT BALANCE CIRCUIT FOR SERIES CELLS' [patent_app_type] => utility [patent_app_number] => 13/934245 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 3916 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13934245 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/934245
Two-way direct balance circuit for series cells Jul 2, 2013 Issued
Array ( [id] => 11223363 [patent_doc_number] => 09451723 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-20 [patent_title] => 'System and method for thermoelectrically cooling inductive charging assemblies' [patent_app_type] => utility [patent_app_number] => 13/935321 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 21 [patent_no_of_words] => 13972 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935321 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935321
System and method for thermoelectrically cooling inductive charging assemblies Jul 2, 2013 Issued
Array ( [id] => 11215233 [patent_doc_number] => 09444276 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-13 [patent_title] => 'Mobile terminal capable of being charged in a wired or wireless manner' [patent_app_type] => utility [patent_app_number] => 13/935159 [patent_app_country] => US [patent_app_date] => 2013-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 20 [patent_no_of_words] => 21312 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13935159 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/935159
Mobile terminal capable of being charged in a wired or wireless manner Jul 2, 2013 Issued
Array ( [id] => 9783506 [patent_doc_number] => 20140300326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-10-09 [patent_title] => 'ELECTRONIC DEVICE WITH A DUTY CYCLE ESTIMATOR' [patent_app_type] => utility [patent_app_number] => 13/933834 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6112 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13933834 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/933834
ELECTRONIC DEVICE WITH A DUTY CYCLE ESTIMATOR Jul 1, 2013 Abandoned
Array ( [id] => 9558348 [patent_doc_number] => 20140176060 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-06-26 [patent_title] => 'Miniature Low-Power Remote Battery Charging Systems and Methods' [patent_app_type] => utility [patent_app_number] => 13/934165 [patent_app_country] => US [patent_app_date] => 2013-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6372 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13934165 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/934165
Miniature Low-Power Remote Battery Charging Systems and Methods Jul 1, 2013 Abandoned
Array ( [id] => 9283195 [patent_doc_number] => 20140033163 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2014-01-30 [patent_title] => 'MODELING GATE SIZE RANGE IN A NUMERICAL GATE SIZING FRAMEWORK' [patent_app_type] => utility [patent_app_number] => 13/931641 [patent_app_country] => US [patent_app_date] => 2013-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 8648 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13931641 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/931641
Modeling gate size range by using a penalty function in a numerical gate sizing framework Jun 27, 2013 Issued
Array ( [id] => 9051374 [patent_doc_number] => 20130249088 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-09-26 [patent_title] => 'ADAPTIVE PATTERNING FOR PANELIZED PACKAGING' [patent_app_type] => utility [patent_app_number] => 13/893117 [patent_app_country] => US [patent_app_date] => 2013-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6451 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13893117 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/893117
Adaptive patterning for panelized packaging May 12, 2013 Issued
Array ( [id] => 10165282 [patent_doc_number] => 09196509 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Semiconductor device and method of adaptive patterning for panelized packaging' [patent_app_type] => utility [patent_app_number] => 13/891006 [patent_app_country] => US [patent_app_date] => 2013-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 46 [patent_no_of_words] => 22196 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13891006 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/891006
Semiconductor device and method of adaptive patterning for panelized packaging May 8, 2013 Issued
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