Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8868331 [patent_doc_number] => 20130152034 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-06-13 [patent_title] => 'SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING' [patent_app_type] => utility [patent_app_number] => 13/315519 [patent_app_country] => US [patent_app_date] => 2011-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3007 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13315519 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/315519
SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING Dec 8, 2011 Abandoned
Array ( [id] => 8568856 [patent_doc_number] => 20120331427 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-27 [patent_title] => 'IN-SITU SCANNER EXPOSURE MONITOR' [patent_app_type] => utility [patent_app_number] => 13/313749 [patent_app_country] => US [patent_app_date] => 2011-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 29 [patent_no_of_words] => 13803 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13313749 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/313749
Predicting pattern critical dimensions in a lithographic exposure process Dec 6, 2011 Issued
Array ( [id] => 9102873 [patent_doc_number] => 08566767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-22 [patent_title] => 'System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation' [patent_app_type] => utility [patent_app_number] => 13/304015 [patent_app_country] => US [patent_app_date] => 2011-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 13527 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13304015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/304015
System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation Nov 22, 2011 Issued
Array ( [id] => 11764522 [patent_doc_number] => 09372949 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-06-21 [patent_title] => 'Guided exploration of circuit design states' [patent_app_type] => utility [patent_app_number] => 13/280955 [patent_app_country] => US [patent_app_date] => 2011-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5164 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13280955 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/280955
Guided exploration of circuit design states Oct 24, 2011 Issued
Array ( [id] => 8769536 [patent_doc_number] => 20130097573 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'ALIGNMENT NET INSERTION FOR STRAIGHTENING THE DATAPATH IN A FORCE-DIRECTED PLACER' [patent_app_type] => utility [patent_app_number] => 13/275105 [patent_app_country] => US [patent_app_date] => 2011-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 7261 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13275105 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/275105
Alignment net insertion for straightening the datapath in a force-directed placer Oct 16, 2011 Issued
Array ( [id] => 8769531 [patent_doc_number] => 20130097568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-04-18 [patent_title] => 'GLOBAL CLOCK HANDLER OBJECT FOR HDL ENVIRONMENT' [patent_app_type] => utility [patent_app_number] => 13/274015 [patent_app_country] => US [patent_app_date] => 2011-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3591 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13274015 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/274015
GLOBAL CLOCK HANDLER OBJECT FOR HDL ENVIRONMENT Oct 13, 2011 Abandoned
Array ( [id] => 10165989 [patent_doc_number] => 09197225 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Control voltage mirror circuit' [patent_app_type] => utility [patent_app_number] => 13/253395 [patent_app_country] => US [patent_app_date] => 2011-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 3085 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13253395 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/253395
Control voltage mirror circuit Oct 4, 2011 Issued
Array ( [id] => 8716269 [patent_doc_number] => 08402423 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'System and method for verifying PCB layout' [patent_app_type] => utility [patent_app_number] => 13/244625 [patent_app_country] => US [patent_app_date] => 2011-09-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2297 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13244625 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/244625
System and method for verifying PCB layout Sep 24, 2011 Issued
Array ( [id] => 8985296 [patent_doc_number] => 08516426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-08-20 [patent_title] => 'Vertical power budgeting and shifting for three-dimensional integration' [patent_app_type] => utility [patent_app_number] => 13/217429 [patent_app_country] => US [patent_app_date] => 2011-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7025 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 176 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13217429 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/217429
Vertical power budgeting and shifting for three-dimensional integration Aug 24, 2011 Issued
Array ( [id] => 9444362 [patent_doc_number] => 08713498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-04-29 [patent_title] => 'Method and system for physical verification using network segment current' [patent_app_type] => utility [patent_app_number] => 13/216769 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 8167 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13216769 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/216769
Method and system for physical verification using network segment current Aug 23, 2011 Issued
Array ( [id] => 7793150 [patent_doc_number] => 20120054706 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-03-01 [patent_title] => 'Timing analysis method, program and system' [patent_app_type] => utility [patent_app_number] => 13/137539 [patent_app_country] => US [patent_app_date] => 2011-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5604 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0054/20120054706.pdf [firstpage_image] =>[orig_patent_app_number] => 13137539 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/137539
Timing analysis method, program and system Aug 23, 2011 Abandoned
Array ( [id] => 10556427 [patent_doc_number] => 09280628 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-03-08 [patent_title] => 'System and method for clock network meta-synthesis' [patent_app_type] => utility [patent_app_number] => 13/214859 [patent_app_country] => US [patent_app_date] => 2011-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 7023 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214859 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214859
System and method for clock network meta-synthesis Aug 21, 2011 Issued
Array ( [id] => 10178071 [patent_doc_number] => 09208277 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2015-12-08 [patent_title] => 'Automated adjustment of wire connections in computer-assisted design of circuits' [patent_app_type] => utility [patent_app_number] => 13/214119 [patent_app_country] => US [patent_app_date] => 2011-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 19 [patent_no_of_words] => 10095 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13214119 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/214119
Automated adjustment of wire connections in computer-assisted design of circuits Aug 18, 2011 Issued
Array ( [id] => 8752276 [patent_doc_number] => 08418120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-09 [patent_title] => 'Solutions for netlist reduction for multi-finger devices' [patent_app_type] => utility [patent_app_number] => 13/188129 [patent_app_country] => US [patent_app_date] => 2011-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9840 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13188129 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/188129
Solutions for netlist reduction for multi-finger devices Jul 20, 2011 Issued
Array ( [id] => 8775614 [patent_doc_number] => 08429590 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'System-level method for reducing power supply noise in an electronic system' [patent_app_type] => utility [patent_app_number] => 13/184909 [patent_app_country] => US [patent_app_date] => 2011-07-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4671 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13184909 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/184909
System-level method for reducing power supply noise in an electronic system Jul 17, 2011 Issued
Array ( [id] => 8611583 [patent_doc_number] => 20130016895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2013-01-17 [patent_title] => 'METHOD AND SYSTEM FOR DEFECT-BITMAP-FAIL PATTERNS MATCHING ANALYSIS INCLUDING PERIPHERAL DEFECTS' [patent_app_type] => utility [patent_app_number] => 13/183899 [patent_app_country] => US [patent_app_date] => 2011-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 3562 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13183899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/183899
METHOD AND SYSTEM FOR DEFECT-BITMAP-FAIL PATTERNS MATCHING ANALYSIS INCLUDING PERIPHERAL DEFECTS Jul 14, 2011 Abandoned
Array ( [id] => 8763381 [patent_doc_number] => 08423920 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Method of forming photomask by collecting verification data based on a layout of contour patterns' [patent_app_type] => utility [patent_app_number] => 13/167949 [patent_app_country] => US [patent_app_date] => 2011-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7174 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13167949 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/167949
Method of forming photomask by collecting verification data based on a layout of contour patterns Jun 23, 2011 Issued
Array ( [id] => 7714485 [patent_doc_number] => 20120005641 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-01-05 [patent_title] => 'SEMICONDUCTOR DESIGNING APPARATUS' [patent_app_type] => utility [patent_app_number] => 13/166349 [patent_app_country] => US [patent_app_date] => 2011-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 7570 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0005/20120005641.pdf [firstpage_image] =>[orig_patent_app_number] => 13166349 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/166349
SEMICONDUCTOR DESIGNING APPARATUS Jun 21, 2011 Abandoned
Array ( [id] => 10079200 [patent_doc_number] => 09117048 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-08-25 [patent_title] => 'Semiconductor integrating circuit layout pattern generating apparatus and method' [patent_app_type] => utility [patent_app_number] => 13/162079 [patent_app_country] => US [patent_app_date] => 2011-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 30 [patent_no_of_words] => 9012 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13162079 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/162079
Semiconductor integrating circuit layout pattern generating apparatus and method Jun 15, 2011 Issued
Array ( [id] => 8518115 [patent_doc_number] => 20120317523 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-12-13 [patent_title] => 'Reducing Through Process Delay Variation in Metal Wires' [patent_app_type] => utility [patent_app_number] => 13/157909 [patent_app_country] => US [patent_app_date] => 2011-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5646 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13157909 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/157909
Reducing through process delay variation in metal wires Jun 9, 2011 Issued
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