
Annette M. Thompson
Examiner (ID: 2883)
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2851, 2825, 2768, 2763 |
| Total Applications | 514 |
| Issued Applications | 410 |
| Pending Applications | 13 |
| Abandoned Applications | 92 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 8868331
[patent_doc_number] => 20130152034
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[patent_kind] => A1
[patent_issue_date] => 2013-06-13
[patent_title] => 'SYSTEM AND METHOD FOR REDUCING INTEGRATED CIRCUIT TIMING DERATING'
[patent_app_type] => utility
[patent_app_number] => 13/315519
[patent_app_country] => US
[patent_app_date] => 2011-12-09
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Array
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[patent_kind] => A1
[patent_issue_date] => 2012-12-27
[patent_title] => 'IN-SITU SCANNER EXPOSURE MONITOR'
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Array
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[patent_title] => 'System and method for parametric intercoupling of static and dynamic analyses for synergistic integration in electronic design automation'
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Array
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[patent_title] => 'Guided exploration of circuit design states'
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Array
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Array
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[patent_title] => 'GLOBAL CLOCK HANDLER OBJECT FOR HDL ENVIRONMENT'
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/253395 | Control voltage mirror circuit | Oct 4, 2011 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 13/244625 | System and method for verifying PCB layout | Sep 24, 2011 | Issued |
Array
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Array
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Array
(
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Array
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Array
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Array
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Array
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