Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 9116337 [patent_doc_number] => 08572529 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-10-29 [patent_title] => 'System and method for dynamically injecting errors to a user design' [patent_app_type] => utility [patent_app_number] => 13/156179 [patent_app_country] => US [patent_app_date] => 2011-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5407 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 108 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13156179 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/156179
System and method for dynamically injecting errors to a user design Jun 7, 2011 Issued
Array ( [id] => 7653279 [patent_doc_number] => 20110302548 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-08 [patent_title] => 'DELAY LIBRARY GENERATION DEVICE AND METHOD' [patent_app_type] => utility [patent_app_number] => 13/151589 [patent_app_country] => US [patent_app_date] => 2011-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 20603 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0302/20110302548.pdf [firstpage_image] =>[orig_patent_app_number] => 13151589 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/151589
DELAY LIBRARY GENERATION DEVICE AND METHOD Jun 1, 2011 Abandoned
Array ( [id] => 8810453 [patent_doc_number] => 08448120 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-21 [patent_title] => 'RC extraction for single patterning spacer technique' [patent_app_type] => utility [patent_app_number] => 13/045839 [patent_app_country] => US [patent_app_date] => 2011-05-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 15 [patent_no_of_words] => 6580 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13045839 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/045839
RC extraction for single patterning spacer technique May 8, 2011 Issued
Array ( [id] => 8805024 [patent_doc_number] => 08443308 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-05-14 [patent_title] => 'EUV lithography flare calculation and compensation' [patent_app_type] => utility [patent_app_number] => 13/098495 [patent_app_country] => US [patent_app_date] => 2011-05-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5377 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13098495 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/098495
EUV lithography flare calculation and compensation May 1, 2011 Issued
Array ( [id] => 9023639 [patent_doc_number] => 08533638 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-09-10 [patent_title] => 'Post-optical proximity correction photoresist pattern collapse rule' [patent_app_type] => utility [patent_app_number] => 13/079869 [patent_app_country] => US [patent_app_date] => 2011-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2291 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13079869 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/079869
Post-optical proximity correction photoresist pattern collapse rule Apr 4, 2011 Issued
Array ( [id] => 8315099 [patent_doc_number] => 20120192126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'SYSTEMS AND METHODS PROVIDING ELECTRON BEAM PROXIMITY EFFECT CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/011165 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011165 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011165
Providing electron beam proximity effect correction by simulating write operations of polygonal shapes Jan 20, 2011 Issued
Array ( [id] => 8315099 [patent_doc_number] => 20120192126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-07-26 [patent_title] => 'SYSTEMS AND METHODS PROVIDING ELECTRON BEAM PROXIMITY EFFECT CORRECTION' [patent_app_type] => utility [patent_app_number] => 13/011165 [patent_app_country] => US [patent_app_date] => 2011-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4037 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13011165 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/011165
Providing electron beam proximity effect correction by simulating write operations of polygonal shapes Jan 20, 2011 Issued
Array ( [id] => 5960939 [patent_doc_number] => 20110185326 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'NET LIST GENERATION METHOD AND CIRCUIT SIMULATION METHOD' [patent_app_type] => utility [patent_app_number] => 13/005255 [patent_app_country] => US [patent_app_date] => 2011-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 7955 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0185/20110185326.pdf [firstpage_image] =>[orig_patent_app_number] => 13005255 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/005255
NET LIST GENERATION METHOD AND CIRCUIT SIMULATION METHOD Jan 11, 2011 Abandoned
Array ( [id] => 8267603 [patent_doc_number] => 20120167033 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'Controlling Plating Stub Reflections In A Chip Package' [patent_app_type] => utility [patent_app_number] => 12/979745 [patent_app_country] => US [patent_app_date] => 2010-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5167 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12979745 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/979745
Controlling plating stub reflections in a chip package Dec 27, 2010 Issued
Array ( [id] => 8267598 [patent_doc_number] => 20120167025 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-28 [patent_title] => 'METHOD FOR ANALYZING SENSITIVITY AND FAILURE PROBABILITY OF A CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/975585 [patent_app_country] => US [patent_app_date] => 2010-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2960 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12975585 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/975585
Method for analyzing sensitivity and failure probability of a circuit Dec 21, 2010 Issued
Array ( [id] => 8703967 [patent_doc_number] => 08397204 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-12 [patent_title] => 'System and methodology for development of a system architecture using optimization parameters' [patent_app_type] => utility [patent_app_number] => 12/974925 [patent_app_country] => US [patent_app_date] => 2010-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 27647 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 481 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12974925 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/974925
System and methodology for development of a system architecture using optimization parameters Dec 20, 2010 Issued
Array ( [id] => 5976981 [patent_doc_number] => 20110154273 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE' [patent_app_type] => utility [patent_app_number] => 12/964185 [patent_app_country] => US [patent_app_date] => 2010-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7715 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154273.pdf [firstpage_image] =>[orig_patent_app_number] => 12964185 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/964185
METHOD OF GENERATING MASK PATTERN, MASK PATTERN GENERATING PROGRAM, AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE Dec 8, 2010 Abandoned
Array ( [id] => 6167149 [patent_doc_number] => 20110161903 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-30 [patent_title] => 'VERIFICATION SUPPORT COMPUTER PRODUCT AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/962785 [patent_app_country] => US [patent_app_date] => 2010-12-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 10592 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20110161903.pdf [firstpage_image] =>[orig_patent_app_number] => 12962785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/962785
Clock domain crossing verification support Dec 7, 2010 Issued
Array ( [id] => 5956623 [patent_doc_number] => 20110181351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-07-28 [patent_title] => 'Application Specific Power Controller' [patent_app_type] => utility [patent_app_number] => 12/961095 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6095 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0181/20110181351.pdf [firstpage_image] =>[orig_patent_app_number] => 12961095 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961095
Application specific power controller configuration technique Dec 5, 2010 Issued
Array ( [id] => 8230156 [patent_doc_number] => 20120144359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-06-07 [patent_title] => 'CYCLE CUTTING WITH TIMING PATH ANALYSIS' [patent_app_type] => utility [patent_app_number] => 12/961355 [patent_app_country] => US [patent_app_date] => 2010-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7686 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12961355 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/961355
Cycle cutting with timing path analysis Dec 5, 2010 Issued
Array ( [id] => 8491583 [patent_doc_number] => 20120290990 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-11-15 [patent_title] => 'Pattern Measuring Condition Setting Device' [patent_app_type] => utility [patent_app_number] => 13/519356 [patent_app_country] => US [patent_app_date] => 2010-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8486 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13519356 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/519356
Pattern Measuring Condition Setting Device Nov 30, 2010 Abandoned
Array ( [id] => 8849429 [patent_doc_number] => 08458629 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-06-04 [patent_title] => 'Decision modules in integrated circuit design' [patent_app_type] => utility [patent_app_number] => 12/954575 [patent_app_country] => US [patent_app_date] => 2010-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 25 [patent_no_of_words] => 14464 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12954575 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/954575
Decision modules in integrated circuit design Nov 23, 2010 Issued
Array ( [id] => 8716267 [patent_doc_number] => 08402420 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Designing an optimal wiring topology for electromigration avoidance' [patent_app_type] => utility [patent_app_number] => 12/926505 [patent_app_country] => US [patent_app_date] => 2010-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 6599 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12926505 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/926505
Designing an optimal wiring topology for electromigration avoidance Nov 22, 2010 Issued
Array ( [id] => 8201988 [patent_doc_number] => 20120124541 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'IMPLEMENTING SPARE LATCH PLACEMENT QUALITY DETERMINATION' [patent_app_type] => utility [patent_app_number] => 12/948165 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3090 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124541.pdf [firstpage_image] =>[orig_patent_app_number] => 12948165 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948165
Implementing spare latch placement quality determination Nov 16, 2010 Issued
Array ( [id] => 8202001 [patent_doc_number] => 20120124536 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'METHOD AND SYSTEM FOR AUTOMATIC GENERATION OF SOLUTIONS FOR CIRCUIT DESIGN RULE VIOLATIONS' [patent_app_type] => utility [patent_app_number] => 12/948755 [patent_app_country] => US [patent_app_date] => 2010-11-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 17757 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124536.pdf [firstpage_image] =>[orig_patent_app_number] => 12948755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/948755
Method and system for automatic generation of solutions for circuit design rule violations Nov 16, 2010 Issued
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