Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8201987 [patent_doc_number] => 20120124539 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-05-17 [patent_title] => 'Clock Optimization with Local Clock Buffer Control Optimization' [patent_app_type] => utility [patent_app_number] => 12/947445 [patent_app_country] => US [patent_app_date] => 2010-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 5451 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20120124539.pdf [firstpage_image] =>[orig_patent_app_number] => 12947445 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/947445
Clock optimization with local clock buffer control optimization Nov 15, 2010 Issued
Array ( [id] => 5976648 [patent_doc_number] => 20110154110 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'Verifying a Register-Transfer Level Design of an Execution Unit' [patent_app_type] => utility [patent_app_number] => 12/946325 [patent_app_country] => US [patent_app_date] => 2010-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3881 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154110.pdf [firstpage_image] =>[orig_patent_app_number] => 12946325 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/946325
Verifying a register-transfer level design of an execution unit Nov 14, 2010 Issued
Array ( [id] => 6057672 [patent_doc_number] => 20110113392 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-12 [patent_title] => 'PROTECTION OF INTELLECTUAL PROPERTY (IP) CORES THROUGH A DESIGN FLOW' [patent_app_type] => utility [patent_app_number] => 12/942675 [patent_app_country] => US [patent_app_date] => 2010-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 14365 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20110113392.pdf [firstpage_image] =>[orig_patent_app_number] => 12942675 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/942675
Protection of intellectual property cores through a design flow Nov 8, 2010 Issued
Array ( [id] => 8355168 [patent_doc_number] => 08250513 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-21 [patent_title] => 'Parallel process optimized signal routing' [patent_app_type] => utility [patent_app_number] => 12/939765 [patent_app_country] => US [patent_app_date] => 2010-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12939765 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/939765
Parallel process optimized signal routing Nov 3, 2010 Issued
Array ( [id] => 9143585 [patent_doc_number] => 08584067 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-12 [patent_title] => 'Clock domain crossing buffer' [patent_app_type] => utility [patent_app_number] => 12/938125 [patent_app_country] => US [patent_app_date] => 2010-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 18 [patent_no_of_words] => 11430 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12938125 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/938125
Clock domain crossing buffer Nov 1, 2010 Issued
Array ( [id] => 9156913 [patent_doc_number] => 08589827 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-11-19 [patent_title] => 'Photoresist simulation' [patent_app_type] => utility [patent_app_number] => 12/915455 [patent_app_country] => US [patent_app_date] => 2010-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4166 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12915455 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/915455
Photoresist simulation Oct 28, 2010 Issued
Array ( [id] => 8372595 [patent_doc_number] => 20120221991 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-30 [patent_title] => 'Interactive Method and Apparatus for Detecting Texted Metal Short Circuits' [patent_app_type] => utility [patent_app_number] => 13/504439 [patent_app_country] => US [patent_app_date] => 2010-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4135 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13504439 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/504439
Interactive Method and Apparatus for Detecting Texted Metal Short Circuits Oct 26, 2010 Abandoned
Array ( [id] => 8412694 [patent_doc_number] => 08276107 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-09-25 [patent_title] => 'Integrated data model based framework for driving design convergence from architecture optimization to physical design closure' [patent_app_type] => utility [patent_app_number] => 12/906785 [patent_app_country] => US [patent_app_date] => 2010-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 5589 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12906785 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/906785
Integrated data model based framework for driving design convergence from architecture optimization to physical design closure Oct 17, 2010 Issued
Array ( [id] => 6040780 [patent_doc_number] => 20110093829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-21 [patent_title] => 'COMPUTER PRODUCT, DESIGN SUPPORT APPARATUS, AND DESIGN SUPPORT METHOD' [patent_app_type] => utility [patent_app_number] => 12/904409 [patent_app_country] => US [patent_app_date] => 2010-10-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 85 [patent_figures_cnt] => 85 [patent_no_of_words] => 32120 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0093/20110093829.pdf [firstpage_image] =>[orig_patent_app_number] => 12904409 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/904409
COMPUTER PRODUCT, DESIGN SUPPORT APPARATUS, AND DESIGN SUPPORT METHOD Oct 13, 2010 Abandoned
Array ( [id] => 8716268 [patent_doc_number] => 08402421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-19 [patent_title] => 'Method and system for subnet defect diagnostics through fault compositing' [patent_app_type] => utility [patent_app_number] => 12/903035 [patent_app_country] => US [patent_app_date] => 2010-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8645 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12903035 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/903035
Method and system for subnet defect diagnostics through fault compositing Oct 11, 2010 Issued
Array ( [id] => 8130811 [patent_doc_number] => 20120089953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-12 [patent_title] => 'MASK LAYOUT FORMATION' [patent_app_type] => utility [patent_app_number] => 12/901595 [patent_app_country] => US [patent_app_date] => 2010-10-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 3819 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0089/20120089953.pdf [firstpage_image] =>[orig_patent_app_number] => 12901595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/901595
Mask layout formation Oct 10, 2010 Issued
Array ( [id] => 6131616 [patent_doc_number] => 20110088004 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-04-14 [patent_title] => 'TOOL IDENTIFYING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/899695 [patent_app_country] => US [patent_app_date] => 2010-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 6744 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0088/20110088004.pdf [firstpage_image] =>[orig_patent_app_number] => 12899695 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/899695
TOOL IDENTIFYING METHOD AND APPARATUS Oct 6, 2010 Abandoned
Array ( [id] => 8703951 [patent_doc_number] => 08397188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-03-12 [patent_title] => 'Systems and methods for testing a component by using encapsulation' [patent_app_type] => utility [patent_app_number] => 12/886835 [patent_app_country] => US [patent_app_date] => 2010-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 12009 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12886835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/886835
Systems and methods for testing a component by using encapsulation Sep 20, 2010 Issued
Array ( [id] => 9781493 [patent_doc_number] => 08856717 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-10-07 [patent_title] => 'Shielded pattern generation for a circuit design board' [patent_app_type] => utility [patent_app_number] => 12/883445 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 65 [patent_figures_cnt] => 66 [patent_no_of_words] => 28053 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12883445 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883445
Shielded pattern generation for a circuit design board Sep 15, 2010 Issued
Array ( [id] => 9458714 [patent_doc_number] => 08719741 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-05-06 [patent_title] => 'Guarding logic inserting method based on gated clock enable signals' [patent_app_type] => utility [patent_app_number] => 12/883835 [patent_app_country] => US [patent_app_date] => 2010-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 25 [patent_no_of_words] => 8977 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 243 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12883835 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/883835
Guarding logic inserting method based on gated clock enable signals Sep 15, 2010 Issued
Array ( [id] => 6020842 [patent_doc_number] => 20110225559 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-09-15 [patent_title] => 'LOGIC VERIFYING APPARATUS, LOGIC VERIFYING METHOD, AND MEDIUM' [patent_app_type] => utility [patent_app_number] => 12/881035 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5193 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0225/20110225559.pdf [firstpage_image] =>[orig_patent_app_number] => 12881035 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/881035
LOGIC VERIFYING APPARATUS, LOGIC VERIFYING METHOD, AND MEDIUM Sep 12, 2010 Abandoned
Array ( [id] => 10596551 [patent_doc_number] => 09317641 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-04-19 [patent_title] => 'Gate substitution based system and method for integrated circuit power and timing optimization' [patent_app_type] => utility [patent_app_number] => 12/880275 [patent_app_country] => US [patent_app_date] => 2010-09-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 9 [patent_no_of_words] => 5485 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12880275 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/880275
Gate substitution based system and method for integrated circuit power and timing optimization Sep 12, 2010 Issued
Array ( [id] => 9630152 [patent_doc_number] => 08799845 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-08-05 [patent_title] => 'Adaptive patterning for panelized packaging' [patent_app_type] => utility [patent_app_number] => 12/876915 [patent_app_country] => US [patent_app_date] => 2010-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 14 [patent_no_of_words] => 6842 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12876915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/876915
Adaptive patterning for panelized packaging Sep 6, 2010 Issued
Array ( [id] => 8775613 [patent_doc_number] => 08429589 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-23 [patent_title] => 'Generating net routing constraints for place and route' [patent_app_type] => utility [patent_app_number] => 12/875755 [patent_app_country] => US [patent_app_date] => 2010-09-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4937 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12875755 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/875755
Generating net routing constraints for place and route Sep 2, 2010 Issued
Array ( [id] => 7760151 [patent_doc_number] => 20120030642 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-02-02 [patent_title] => 'HYPER-CONCURRENT MULTI-SCENARIO OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/845545 [patent_app_country] => US [patent_app_date] => 2010-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9341 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0030/20120030642.pdf [firstpage_image] =>[orig_patent_app_number] => 12845545 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/845545
Hyper-concurrent optimization over multi-corner multi-mode scenarios Jul 27, 2010 Issued
Menu