Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8391254 [patent_doc_number] => 20120229099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-09-13 [patent_title] => 'System for Storing Electrical Energy' [patent_app_type] => utility [patent_app_number] => 13/391616 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4357 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391616 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/391616
System for Storing Electrical Energy Jul 15, 2010 Abandoned
Array ( [id] => 8333560 [patent_doc_number] => 20120200267 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'System for Storing Electric Energy' [patent_app_type] => utility [patent_app_number] => 13/391611 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3889 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13391611 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/391611
System for Storing Electric Energy Jul 15, 2010 Abandoned
Array ( [id] => 8333552 [patent_doc_number] => 20120200261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-08-09 [patent_title] => 'System for Storing Electric Energy' [patent_app_type] => utility [patent_app_number] => 13/390481 [patent_app_country] => US [patent_app_date] => 2010-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6426 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13390481 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/390481
System for Storing Electric Energy Jul 15, 2010 Abandoned
Array ( [id] => 6198179 [patent_doc_number] => 20110029937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-03 [patent_title] => 'PATTERN EVALUATING METHOD, PATTERN GENERATING METHOD, AND COMPUTER PROGRAM PRODUCT' [patent_app_type] => utility [patent_app_number] => 12/836235 [patent_app_country] => US [patent_app_date] => 2010-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 11440 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0029/20110029937.pdf [firstpage_image] =>[orig_patent_app_number] => 12836235 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/836235
PATTERN EVALUATING METHOD, PATTERN GENERATING METHOD, AND COMPUTER PROGRAM PRODUCT Jul 13, 2010 Abandoned
Array ( [id] => 6364745 [patent_doc_number] => 20100333054 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-30 [patent_title] => 'CIRCUIT DESIGN ASSISTING APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/814739 [patent_app_country] => US [patent_app_date] => 2010-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 13563 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0333/20100333054.pdf [firstpage_image] =>[orig_patent_app_number] => 12814739 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/814739
CIRCUIT DESIGN ASSISTING APPARATUS Jun 13, 2010 Abandoned
Array ( [id] => 10501646 [patent_doc_number] => 09230047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-01-05 [patent_title] => 'Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement' [patent_app_type] => utility [patent_app_number] => 12/802669 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7958 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12802669 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/802669
Method and apparatus for partitioning a synthesis netlist for compile time and quality of results improvement Jun 10, 2010 Issued
Array ( [id] => 6032141 [patent_doc_number] => 20110055778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-03 [patent_title] => 'Automatic Application-Rule Checker' [patent_app_type] => utility [patent_app_number] => 12/813849 [patent_app_country] => US [patent_app_date] => 2010-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3177 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0055/20110055778.pdf [firstpage_image] =>[orig_patent_app_number] => 12813849 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/813849
Automatic application-rule checker Jun 10, 2010 Issued
Array ( [id] => 6645107 [patent_doc_number] => 20100313175 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-12-09 [patent_title] => 'VERIFICATION SYSTEMS AND METHODS' [patent_app_type] => utility [patent_app_number] => 12/793719 [patent_app_country] => US [patent_app_date] => 2010-06-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6232 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0313/20100313175.pdf [firstpage_image] =>[orig_patent_app_number] => 12793719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/793719
VERIFICATION SYSTEMS AND METHODS Jun 3, 2010 Abandoned
Array ( [id] => 10164565 [patent_doc_number] => 09195791 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2015-11-24 [patent_title] => 'Custom module generation' [patent_app_type] => utility [patent_app_number] => 12/791759 [patent_app_country] => US [patent_app_date] => 2010-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 4282 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 234 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12791759 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/791759
Custom module generation May 31, 2010 Issued
Array ( [id] => 7582477 [patent_doc_number] => 20110296360 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'METHOD FOR CHECKING AND FIXING DOUBLE-PATTERNING LAYOUT' [patent_app_type] => utility [patent_app_number] => 12/788789 [patent_app_country] => US [patent_app_date] => 2010-05-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 17 [patent_no_of_words] => 6471 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296360.pdf [firstpage_image] =>[orig_patent_app_number] => 12788789 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/788789
Method for checking and fixing double-patterning layout May 26, 2010 Issued
Array ( [id] => 6074268 [patent_doc_number] => 20110047522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-02-24 [patent_title] => 'Hardware Description Language Editing Engine' [patent_app_type] => utility [patent_app_number] => 12/785419 [patent_app_country] => US [patent_app_date] => 2010-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3863 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0047/20110047522.pdf [firstpage_image] =>[orig_patent_app_number] => 12785419 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/785419
Hardware Description Language Editing Engine May 20, 2010 Abandoned
Array ( [id] => 7569401 [patent_doc_number] => 20110289464 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-11-24 [patent_title] => 'GLOBAL TIMING MODELING WITHIN A LOCAL CONTEXT' [patent_app_type] => utility [patent_app_number] => 12/783915 [patent_app_country] => US [patent_app_date] => 2010-05-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0289/20110289464.pdf [firstpage_image] =>[orig_patent_app_number] => 12783915 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/783915
Global timing modeling within a local context May 19, 2010 Issued
Array ( [id] => 6366274 [patent_doc_number] => 20100251200 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'VIA DESIGN APPARATUS AND VIA DESIGN METHOD' [patent_app_type] => utility [patent_app_number] => 12/781009 [patent_app_country] => US [patent_app_date] => 2010-05-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 2903 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0251/20100251200.pdf [firstpage_image] =>[orig_patent_app_number] => 12781009 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/781009
Via design apparatus and via design method based on impedance calculations May 16, 2010 Issued
Array ( [id] => 6596214 [patent_doc_number] => 20100275170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-10-28 [patent_title] => 'Porting Analog Circuit Designs' [patent_app_type] => utility [patent_app_number] => 12/768139 [patent_app_country] => US [patent_app_date] => 2010-04-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4617 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0275/20100275170.pdf [firstpage_image] =>[orig_patent_app_number] => 12768139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/768139
Porting Analog Circuit Designs Apr 26, 2010 Abandoned
Array ( [id] => 8143741 [patent_doc_number] => 20120096421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2012-04-19 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT DESIGN APPARATUS, DATA PROCESSING METHOD THEREOF, AND CONTROL PROGRAM THEREOF' [patent_app_type] => utility [patent_app_number] => 13/262759 [patent_app_country] => US [patent_app_date] => 2010-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 7469 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0096/20120096421.pdf [firstpage_image] =>[orig_patent_app_number] => 13262759 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/262759
Semiconductor integrated circuit design apparatus and method for analyzing a delay in a semiconductor integrated circuit Apr 20, 2010 Issued
Array ( [id] => 5996698 [patent_doc_number] => 20110016443 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-01-20 [patent_title] => 'Dummy Pattern Performance Aware Analysis and Implementation' [patent_app_type] => utility [patent_app_number] => 12/763889 [patent_app_country] => US [patent_app_date] => 2010-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4756 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0016/20110016443.pdf [firstpage_image] =>[orig_patent_app_number] => 12763889 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/763889
Dummy pattern performance aware analysis and implementation Apr 19, 2010 Issued
Array ( [id] => 10873392 [patent_doc_number] => 08898614 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-11-25 [patent_title] => 'Integrated circuit device with reduced leakage and method therefor' [patent_app_type] => utility [patent_app_number] => 12/762439 [patent_app_country] => US [patent_app_date] => 2010-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 10333 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12762439 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/762439
Integrated circuit device with reduced leakage and method therefor Apr 18, 2010 Issued
Array ( [id] => 8763400 [patent_doc_number] => 08423939 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-04-16 [patent_title] => 'Boundary buffers to model register incompatibility during pre-retiming optimization' [patent_app_type] => utility [patent_app_number] => 12/754724 [patent_app_country] => US [patent_app_date] => 2010-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 8028 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 263 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12754724 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/754724
Boundary buffers to model register incompatibility during pre-retiming optimization Apr 5, 2010 Issued
Array ( [id] => 8366780 [patent_doc_number] => 08255860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-08-28 [patent_title] => 'Exploiting independent portions of logic designs for timing optimization' [patent_app_type] => utility [patent_app_number] => 12/751809 [patent_app_country] => US [patent_app_date] => 2010-03-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 19 [patent_no_of_words] => 10132 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12751809 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/751809
Exploiting independent portions of logic designs for timing optimization Mar 30, 2010 Issued
Array ( [id] => 6647857 [patent_doc_number] => 20100175036 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'LOGIC CIRCUIT MODEL VERIFYING METHOD AND APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/725709 [patent_app_country] => US [patent_app_date] => 2010-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 7181 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20100175036.pdf [firstpage_image] =>[orig_patent_app_number] => 12725709 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725709
LOGIC CIRCUIT MODEL VERIFYING METHOD AND APPARATUS Mar 16, 2010 Abandoned
Menu