Search

Annette M. Thompson

Examiner (ID: 2883)

Most Active Art Unit
2825
Art Unit(s)
2851, 2825, 2768, 2763
Total Applications
514
Issued Applications
410
Pending Applications
13
Abandoned Applications
92

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 8170991 [patent_doc_number] => 08176449 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-05-08 [patent_title] => 'Inference of hardware components from logic patterns' [patent_app_type] => utility [patent_app_number] => 12/722139 [patent_app_country] => US [patent_app_date] => 2010-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4975 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/176/08176449.pdf [firstpage_image] =>[orig_patent_app_number] => 12722139 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/722139
Inference of hardware components from logic patterns Mar 10, 2010 Issued
Array ( [id] => 8899609 [patent_doc_number] => 08479143 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-07-02 [patent_title] => 'Signature based duplicate extraction' [patent_app_type] => utility [patent_app_number] => 12/720529 [patent_app_country] => US [patent_app_date] => 2010-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 6137 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12720529 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/720529
Signature based duplicate extraction Mar 8, 2010 Issued
Array ( [id] => 8763379 [patent_doc_number] => 08423918 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-04-16 [patent_title] => 'Structure and methodology for fabrication and inspection of photomasks by a single design system' [patent_app_type] => utility [patent_app_number] => 12/719059 [patent_app_country] => US [patent_app_date] => 2010-03-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8827 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12719059 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/719059
Structure and methodology for fabrication and inspection of photomasks by a single design system Mar 7, 2010 Issued
Array ( [id] => 7671727 [patent_doc_number] => 20110320996 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'DELAY LIBRARY GENERATION SYSTEM' [patent_app_type] => utility [patent_app_number] => 13/254335 [patent_app_country] => US [patent_app_date] => 2010-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 6645 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 13254335 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/254335
Delay library generation apparatus and method based on wiring arrangements Feb 25, 2010 Issued
Array ( [id] => 7582479 [patent_doc_number] => 20110296362 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-01 [patent_title] => 'SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION' [patent_app_type] => utility [patent_app_number] => 13/147899 [patent_app_country] => US [patent_app_date] => 2010-02-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 9835 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0296/20110296362.pdf [firstpage_image] =>[orig_patent_app_number] => 13147899 [rel_patent_id] =>[rel_patent_doc_number] =>)
13/147899
SEMICONDUCTOR DEFECT INTEGRATED PROJECTION METHOD AND DEFECT INSPECTION SUPPORT APPARATUS EQUIPPED WITH SEMICONDUCTOR DEFECT INTEGRATED PROJECTION FUNCTION Jan 31, 2010 Abandoned
Array ( [id] => 6006398 [patent_doc_number] => 20110119648 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-19 [patent_title] => 'ROUTING SYSTEM AND METHOD FOR DOUBLE PATTERNING TECHNOLOGY' [patent_app_type] => utility [patent_app_number] => 12/649979 [patent_app_country] => US [patent_app_date] => 2009-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 6406 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0119/20110119648.pdf [firstpage_image] =>[orig_patent_app_number] => 12649979 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/649979
Routing system and method for double patterning technology Dec 29, 2009 Issued
Array ( [id] => 8343231 [patent_doc_number] => 08245169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-08-14 [patent_title] => 'Generating capacitance look-up tables for wiring patterns in the presence of metal fills' [patent_app_type] => utility [patent_app_number] => 12/648456 [patent_app_country] => US [patent_app_date] => 2009-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 13 [patent_no_of_words] => 6193 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12648456 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648456
Generating capacitance look-up tables for wiring patterns in the presence of metal fills Dec 28, 2009 Issued
Array ( [id] => 6449711 [patent_doc_number] => 20100169857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-01 [patent_title] => 'METHOD FOR DESIGNING A HIGH PERFORMANCE ASIC (APPLICATION-SPECIFIC INTEGRATED CIRCUIT) ACCELERATOR' [patent_app_type] => utility [patent_app_number] => 12/648099 [patent_app_country] => US [patent_app_date] => 2009-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 7508 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0169/20100169857.pdf [firstpage_image] =>[orig_patent_app_number] => 12648099 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/648099
Method of designing a high performance application specific integrated circuit accelerator Dec 27, 2009 Issued
Array ( [id] => 10643903 [patent_doc_number] => 09360766 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-06-07 [patent_title] => 'Method and system for lithography process-window-maximixing optical proximity correction' [patent_app_type] => utility [patent_app_number] => 12/642436 [patent_app_country] => US [patent_app_date] => 2009-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 26176 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12642436 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/642436
Method and system for lithography process-window-maximixing optical proximity correction Dec 17, 2009 Issued
Array ( [id] => 5976997 [patent_doc_number] => 20110154280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-23 [patent_title] => 'PROPAGATING DESIGN TOLERANCES TO SHAPE TOLERANCES FOR LITHOGRAPHY' [patent_app_type] => utility [patent_app_number] => 12/640129 [patent_app_country] => US [patent_app_date] => 2009-12-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5961 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0154/20110154280.pdf [firstpage_image] =>[orig_patent_app_number] => 12640129 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/640129
Propagating design tolerances to shape tolerances for lithography Dec 16, 2009 Issued
Array ( [id] => 9326345 [patent_doc_number] => 08661382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2014-02-25 [patent_title] => 'Modeling for soft error specification' [patent_app_type] => utility [patent_app_number] => 12/637016 [patent_app_country] => US [patent_app_date] => 2009-12-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6030 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12637016 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/637016
Modeling for soft error specification Dec 13, 2009 Issued
Array ( [id] => 10536728 [patent_doc_number] => 09262359 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-02-16 [patent_title] => 'Method and system for implementing pipeline flip-flops' [patent_app_type] => utility [patent_app_number] => 12/631376 [patent_app_country] => US [patent_app_date] => 2009-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4555 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12631376 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/631376
Method and system for implementing pipeline flip-flops Dec 3, 2009 Issued
Array ( [id] => 8449296 [patent_doc_number] => 08291366 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-10-16 [patent_title] => 'Routing system and method using a routing tree rip-up' [patent_app_type] => utility [patent_app_number] => 12/630576 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2945 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12630576 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630576
Routing system and method using a routing tree rip-up Dec 2, 2009 Issued
Array ( [id] => 6464701 [patent_doc_number] => 20100146338 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-10 [patent_title] => 'AUTOMATED SEMICONDUCTOR DESIGN FLAW DETECTION SYSTEM' [patent_app_type] => utility [patent_app_number] => 12/630719 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 11790 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0146/20100146338.pdf [firstpage_image] =>[orig_patent_app_number] => 12630719 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630719
Automated semiconductor design flaw detection system Dec 2, 2009 Issued
Array ( [id] => 6647887 [patent_doc_number] => 20100175039 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-07-08 [patent_title] => 'INTEGRATED CIRCUIT DESIGN APPARATUS, DESIGN METHOD, AND STORAGE MEDIA' [patent_app_type] => utility [patent_app_number] => 12/630619 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 7502 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0175/20100175039.pdf [firstpage_image] =>[orig_patent_app_number] => 12630619 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630619
Method and apparatus for scan path connection routing Dec 2, 2009 Issued
Array ( [id] => 6218057 [patent_doc_number] => 20110138342 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-09 [patent_title] => 'Retargeting for Electrical Yield Enhancement' [patent_app_type] => utility [patent_app_number] => 12/630216 [patent_app_country] => US [patent_app_date] => 2009-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 8011 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20110138342.pdf [firstpage_image] =>[orig_patent_app_number] => 12630216 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/630216
Retargeting for electrical yield enhancement Dec 2, 2009 Issued
Array ( [id] => 6253691 [patent_doc_number] => 20100138799 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'ANALYSIS APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/628336 [patent_app_country] => US [patent_app_date] => 2009-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 4174 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0138/20100138799.pdf [firstpage_image] =>[orig_patent_app_number] => 12628336 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628336
Analysis apparatus and method to analyze a printed circuit board Nov 30, 2009 Issued
Array ( [id] => 6147634 [patent_doc_number] => 20110131540 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-06-02 [patent_title] => 'Path Preserving Design Partitioning With Redundancy' [patent_app_type] => utility [patent_app_number] => 12/628096 [patent_app_country] => US [patent_app_date] => 2009-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 7697 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0131/20110131540.pdf [firstpage_image] =>[orig_patent_app_number] => 12628096 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/628096
Path preserving design partitioning with redundancy Nov 29, 2009 Issued
Array ( [id] => 9116336 [patent_doc_number] => 08572528 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2013-10-29 [patent_title] => 'Method and apparatus for analyzing a design of an integrated circuit using fault costs' [patent_app_type] => utility [patent_app_number] => 12/626559 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5060 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12626559 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/626559
Method and apparatus for analyzing a design of an integrated circuit using fault costs Nov 24, 2009 Issued
Array ( [id] => 6185453 [patent_doc_number] => 20110124193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-05-26 [patent_title] => 'CUSTOMIZED PATTERNING MODULATION AND OPTIMIZATION' [patent_app_type] => utility [patent_app_number] => 12/625749 [patent_app_country] => US [patent_app_date] => 2009-11-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 9537 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0124/20110124193.pdf [firstpage_image] =>[orig_patent_app_number] => 12625749 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/625749
Customized patterning modulation and optimization Nov 24, 2009 Issued
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