Search

Anthan Tran

Examiner (ID: 4039, Phone: (571)272-8709 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2827, 2825
Total Applications
1098
Issued Applications
898
Pending Applications
85
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 19726893 [patent_doc_number] => 20250029644 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => MAGNETIC MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/773949 [patent_app_country] => US [patent_app_date] => 2024-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6444 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18773949 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/773949
MAGNETIC MEMORY DEVICE Jul 15, 2024 Pending
Array ( [id] => 19546144 [patent_doc_number] => 20240363180 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 18/768518 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18632 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768518 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/768518
PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY Jul 9, 2024 Pending
Array ( [id] => 19803722 [patent_doc_number] => 20250069647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING ARRAY CONTROL CIRCUIT CONTROLLING SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 18/749464 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749464
SEMICONDUCTOR DEVICE HAVING ARRAY CONTROL CIRCUIT CONTROLLING SENSE AMPLIFIERS Jun 19, 2024 Pending
Array ( [id] => 19749189 [patent_doc_number] => 20250037754 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/749394 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3560 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749394 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749394
SEMICONDUCTOR DEVICE HAVING ROW DECODER CIRCUIT Jun 19, 2024 Pending
Array ( [id] => 19803722 [patent_doc_number] => 20250069647 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => SEMICONDUCTOR DEVICE HAVING ARRAY CONTROL CIRCUIT CONTROLLING SENSE AMPLIFIERS [patent_app_type] => utility [patent_app_number] => 18/749464 [patent_app_country] => US [patent_app_date] => 2024-06-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4055 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18749464 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/749464
SEMICONDUCTOR DEVICE HAVING ARRAY CONTROL CIRCUIT CONTROLLING SENSE AMPLIFIERS Jun 19, 2024 Pending
Array ( [id] => 19893039 [patent_doc_number] => 20250118351 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746226 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12912 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746226 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/746226
APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES Jun 17, 2024 Pending
Array ( [id] => 19712363 [patent_doc_number] => 20250022505 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => LOCAL I/O READ CIRCUIT IN MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/743561 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3932 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743561 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743561
LOCAL I/O READ CIRCUIT IN MEMORY SYSTEM Jun 13, 2024 Pending
Array ( [id] => 20088561 [patent_doc_number] => 20250218497 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/743925 [patent_app_country] => US [patent_app_date] => 2024-06-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18743925 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/743925
MEMORY CORE CIRCUIT HAVING CELL ON PERIPHERY (COP) STRUCTURE AND MEMORY DEVICE INCLUDING THE SAME Jun 13, 2024 Pending
Array ( [id] => 19589376 [patent_doc_number] => 20240386933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-21 [patent_title] => ADJUSTING A SENSING VOLTAGE IN MEMORY [patent_app_type] => utility [patent_app_number] => 18/662313 [patent_app_country] => US [patent_app_date] => 2024-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18662313 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/662313
ADJUSTING A SENSING VOLTAGE IN MEMORY May 12, 2024 Pending
Array ( [id] => 19409080 [patent_doc_number] => 20240292591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-29 [patent_title] => MEMORY DEVICES WITH GATE ALL AROUND TRANSISTORS [patent_app_type] => utility [patent_app_number] => 18/655568 [patent_app_country] => US [patent_app_date] => 2024-05-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8022 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18655568 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/655568
MEMORY DEVICES WITH GATE ALL AROUND TRANSISTORS May 5, 2024 Pending
Array ( [id] => 20088586 [patent_doc_number] => 20250218522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD LINES AND BIT LINES AND TEST METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/652457 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652457
SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD LINES AND BIT LINES AND TEST METHOD FOR THE SAME Apr 30, 2024 Pending
Array ( [id] => 20088586 [patent_doc_number] => 20250218522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD LINES AND BIT LINES AND TEST METHOD FOR THE SAME [patent_app_type] => utility [patent_app_number] => 18/652457 [patent_app_country] => US [patent_app_date] => 2024-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18652457 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/652457
SEMICONDUCTOR DEVICE THAT DETECTS CONNECTION DEFECTS BETWEEN WORD LINES AND BIT LINES AND TEST METHOD FOR THE SAME Apr 30, 2024 Pending
Array ( [id] => 19363929 [patent_doc_number] => 20240265963 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => MEMORY DEVICE WITH IMPROVED DRIVER OPERATION AND METHODS TO OPERATE THE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/637057 [patent_app_country] => US [patent_app_date] => 2024-04-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18637057 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/637057
MEMORY DEVICE WITH IMPROVED DRIVER OPERATION AND METHODS TO OPERATE THE MEMORY DEVICE Apr 15, 2024 Pending
Array ( [id] => 19348893 [patent_doc_number] => 20240257857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 18/635208 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635208 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635208
APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION Apr 14, 2024 Pending
Array ( [id] => 19348893 [patent_doc_number] => 20240257857 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-01 [patent_title] => APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION [patent_app_type] => utility [patent_app_number] => 18/635208 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10379 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635208 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635208
APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION Apr 14, 2024 Pending
Array ( [id] => 19363922 [patent_doc_number] => 20240265956 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-08-08 [patent_title] => MEMORY CHIP AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/635049 [patent_app_country] => US [patent_app_date] => 2024-04-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12934 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18635049 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/635049
Memory chip and operating method thereof Apr 14, 2024 Issued
Array ( [id] => 20080559 [patent_doc_number] => 12354634 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-08 [patent_title] => Transistorless memory cell [patent_app_type] => utility [patent_app_number] => 18/632358 [patent_app_country] => US [patent_app_date] => 2024-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 4231 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18632358 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/632358
Transistorless memory cell Apr 10, 2024 Issued
Array ( [id] => 19515410 [patent_doc_number] => 20240347096 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-17 [patent_title] => Usage-Based Disturbance Counter Clearance [patent_app_type] => utility [patent_app_number] => 18/628127 [patent_app_country] => US [patent_app_date] => 2024-04-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13278 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18628127 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/628127
Usage-Based Disturbance Counter Clearance Apr 4, 2024 Pending
Array ( [id] => 19748014 [patent_doc_number] => 20250036579 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-30 [patent_title] => MEMORY DEVICE WITH MULTIPLE PHYSICAL INTERFACES [patent_app_type] => utility [patent_app_number] => 18/625212 [patent_app_country] => US [patent_app_date] => 2024-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6282 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18625212 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/625212
MEMORY DEVICE WITH MULTIPLE PHYSICAL INTERFACES Apr 2, 2024 Pending
Array ( [id] => 20235506 [patent_doc_number] => 20250292825 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE [patent_app_type] => utility [patent_app_number] => 18/603154 [patent_app_country] => US [patent_app_date] => 2024-03-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18603154 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/603154
DYNAMIC RANDOM-ACCESS MEMORY (DRAM) DEVICE Mar 11, 2024 Pending
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