Search

Anthan Tran

Examiner (ID: 7284, Phone: (571)272-8709 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2825, 2827
Total Applications
1125
Issued Applications
917
Pending Applications
74
Abandoned Applications
152

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17660454 [patent_doc_number] => 20220180919 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => ARTIFICIAL INTELLIGENCE PROCESSOR AND METHOD OF PROCESSING DEEP-LEARNING OPERATION USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/544202 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4252 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 63 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544202 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544202
Artificial intelligence processor and method of processing deep-learning operation using the same Dec 6, 2021 Issued
Array ( [id] => 17660460 [patent_doc_number] => 20220180925 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-09 [patent_title] => SELECTOR DEVICE, RESISTIVE TYPE MEMORY DEVICE AND ASSOCIATED MANUFACTURING METHOD [patent_app_type] => utility [patent_app_number] => 17/544138 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9306 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544138 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544138
SELECTOR DEVICE, RESISTIVE TYPE MEMORY DEVICE AND ASSOCIATED MANUFACTURING METHOD Dec 6, 2021 Abandoned
Array ( [id] => 17645040 [patent_doc_number] => 20220172779 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-02 [patent_title] => PROGRAMMING ENHANCEMENT IN SELF-SELECTING MEMORY [patent_app_type] => utility [patent_app_number] => 17/544679 [patent_app_country] => US [patent_app_date] => 2021-12-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12148 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17544679 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/544679
Programming enhancement in self-selecting memory Dec 6, 2021 Issued
Array ( [id] => 18061444 [patent_doc_number] => 20220392530 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => EARLY DISCHARGE SEQUENCES DURING READ RECOVERY TO ALLEVIATE LATENT READ DISTURB [patent_app_type] => utility [patent_app_number] => 17/540752 [patent_app_country] => US [patent_app_date] => 2021-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9140 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17540752 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/540752
Early discharge sequences during read recovery to alleviate latent read disturb Dec 1, 2021 Issued
Array ( [id] => 18061430 [patent_doc_number] => 20220392516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => NON-VOLATILE MEMORY DEVICE, CONTROLLER FOR CONTROLLING THE SAME, STORAGE DEVICE HAVING THE SAME, AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/535881 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12477 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535881 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535881
Non-volatile memory device, controller for controlling the same, storage device having the same, and method of operating the same Nov 25, 2021 Issued
Array ( [id] => 17764557 [patent_doc_number] => 20220238170 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-07-28 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/535771 [patent_app_country] => US [patent_app_date] => 2021-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11935 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17535771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/535771
Memory system for programming dummy data to a portion of a storage region in a program mode Nov 25, 2021 Issued
Array ( [id] => 18721255 [patent_doc_number] => 11798607 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Asynchronous read circuit using delay sensing in magnetoresistive random access memory (mRAM) [patent_app_type] => utility [patent_app_number] => 17/524125 [patent_app_country] => US [patent_app_date] => 2021-11-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 16 [patent_no_of_words] => 7948 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17524125 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/524125
Asynchronous read circuit using delay sensing in magnetoresistive random access memory (mRAM) Nov 10, 2021 Issued
Array ( [id] => 18781080 [patent_doc_number] => 11822820 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-11-21 [patent_title] => Storage system and method for multi-cell mapping [patent_app_type] => utility [patent_app_number] => 17/523124 [patent_app_country] => US [patent_app_date] => 2021-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 15 [patent_no_of_words] => 5172 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17523124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/523124
Storage system and method for multi-cell mapping Nov 9, 2021 Issued
Array ( [id] => 18401921 [patent_doc_number] => 11664065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-05-30 [patent_title] => Dynamic random-access memory and operation method thereof [patent_app_type] => utility [patent_app_number] => 17/518575 [patent_app_country] => US [patent_app_date] => 2021-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3551 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17518575 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/518575
Dynamic random-access memory and operation method thereof Nov 2, 2021 Issued
Array ( [id] => 18333826 [patent_doc_number] => 20230125774 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-27 [patent_title] => DYNAMIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/510405 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3378 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 236 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17510405 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/510405
DYNAMIC RANDOM ACCESS MEMORY AND OPERATION METHOD THEREOF Oct 25, 2021 Abandoned
Array ( [id] => 19538487 [patent_doc_number] => 12131040 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-29 [patent_title] => Delay of initialization at memory die [patent_app_type] => utility [patent_app_number] => 17/509989 [patent_app_country] => US [patent_app_date] => 2021-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6734 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17509989 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/509989
Delay of initialization at memory die Oct 24, 2021 Issued
Array ( [id] => 18430323 [patent_doc_number] => 11675541 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-13 [patent_title] => Systems and methods for centralized address capture circuitry [patent_app_type] => utility [patent_app_number] => 17/506472 [patent_app_country] => US [patent_app_date] => 2021-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4148 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17506472 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/506472
Systems and methods for centralized address capture circuitry Oct 19, 2021 Issued
Array ( [id] => 17676355 [patent_doc_number] => 20220189522 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-06-16 [patent_title] => MULTI-ACCESS MEMORY CELL [patent_app_type] => utility [patent_app_number] => 17/450231 [patent_app_country] => US [patent_app_date] => 2021-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10563 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17450231 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/450231
MULTI-ACCESS MEMORY CELL Oct 6, 2021 Abandoned
Array ( [id] => 18299969 [patent_doc_number] => 20230109655 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-06 [patent_title] => RECEIVER CIRCUIT, MEMORY DEVICE AND OPERATION METHOD USING THE SAME [patent_app_type] => utility [patent_app_number] => 17/491535 [patent_app_country] => US [patent_app_date] => 2021-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4396 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17491535 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/491535
Receiver circuit, memory device and operation method using the same Sep 30, 2021 Issued
Array ( [id] => 17932975 [patent_doc_number] => 20220328101 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 17/488964 [patent_app_country] => US [patent_app_date] => 2021-09-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11058 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17488964 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/488964
Memory device and operating method for performing a partial program operation Sep 28, 2021 Issued
Array ( [id] => 17932988 [patent_doc_number] => 20220328114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/487705 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487705
Page buffer comprising a bit line controller and latch units Sep 27, 2021 Issued
Array ( [id] => 19244344 [patent_doc_number] => 12014795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Double sense amp and fractional bit assignment in non-volatile memory structures [patent_app_type] => utility [patent_app_number] => 17/486090 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 14966 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486090
Double sense amp and fractional bit assignment in non-volatile memory structures Sep 26, 2021 Issued
Array ( [id] => 17900475 [patent_doc_number] => 20220310137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/483244 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483244
Multi-mode compatible ZQ calibration circuit in memory device Sep 22, 2021 Issued
Array ( [id] => 18304231 [patent_doc_number] => 11626143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Output driver and semiconductor memory device having the same [patent_app_type] => utility [patent_app_number] => 17/481995 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481995
Output driver and semiconductor memory device having the same Sep 21, 2021 Issued
Array ( [id] => 19414521 [patent_doc_number] => 12080355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise [patent_app_type] => utility [patent_app_number] => 17/481225 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481225
Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise Sep 20, 2021 Issued
Menu