Search

Anthan Tran

Examiner (ID: 4039, Phone: (571)272-8709 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2827, 2825
Total Applications
1098
Issued Applications
898
Pending Applications
85
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17932988 [patent_doc_number] => 20220328114 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-13 [patent_title] => PAGE BUFFER, SEMICONDUCTOR MEMORY HAVING THE SAME, AND OPERATING METHOD OF THE SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 17/487705 [patent_app_country] => US [patent_app_date] => 2021-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18619 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17487705 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/487705
Page buffer comprising a bit line controller and latch units Sep 27, 2021 Issued
Array ( [id] => 19244344 [patent_doc_number] => 12014795 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-06-18 [patent_title] => Double sense amp and fractional bit assignment in non-volatile memory structures [patent_app_type] => utility [patent_app_number] => 17/486090 [patent_app_country] => US [patent_app_date] => 2021-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 33 [patent_no_of_words] => 14966 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17486090 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/486090
Double sense amp and fractional bit assignment in non-volatile memory structures Sep 26, 2021 Issued
Array ( [id] => 17900475 [patent_doc_number] => 20220310137 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-29 [patent_title] => MULTI-MODE COMPATIBLE ZQ CALIBRATION CIRCUIT IN MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 17/483244 [patent_app_country] => US [patent_app_date] => 2021-09-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8031 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17483244 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/483244
Multi-mode compatible ZQ calibration circuit in memory device Sep 22, 2021 Issued
Array ( [id] => 18304231 [patent_doc_number] => 11626143 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Output driver and semiconductor memory device having the same [patent_app_type] => utility [patent_app_number] => 17/481995 [patent_app_country] => US [patent_app_date] => 2021-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 9398 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 304 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481995 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481995
Output driver and semiconductor memory device having the same Sep 21, 2021 Issued
Array ( [id] => 19414521 [patent_doc_number] => 12080355 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-03 [patent_title] => Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise [patent_app_type] => utility [patent_app_number] => 17/481225 [patent_app_country] => US [patent_app_date] => 2021-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5204 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17481225 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/481225
Method of improving read current stability in analog non-volatile memory by post-program tuning for memory cells exhibiting random telegraph noise Sep 20, 2021 Issued
Array ( [id] => 18623588 [patent_doc_number] => 11756642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-09-12 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 17/476229 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 34 [patent_no_of_words] => 25789 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476229 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476229
Memory system Sep 14, 2021 Issued
Array ( [id] => 18415837 [patent_doc_number] => 11670382 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-06-06 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 17/476279 [patent_app_country] => US [patent_app_date] => 2021-09-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 13917 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 436 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17476279 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/476279
Memory device Sep 14, 2021 Issued
Array ( [id] => 18255922 [patent_doc_number] => 20230082961 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-16 [patent_title] => HYBRID MEMORY FOR NEUROMORPHIC APPLICATIONS [patent_app_type] => utility [patent_app_number] => 17/472145 [patent_app_country] => US [patent_app_date] => 2021-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6679 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 25 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17472145 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/472145
HYBRID MEMORY FOR NEUROMORPHIC APPLICATIONS Sep 9, 2021 Pending
Array ( [id] => 17582574 [patent_doc_number] => 20220139429 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-05-05 [patent_title] => SENSE AMPLIFIER AND SEMICONDUCTOR MEMORY DEVICE INCLUDING THE SENSE AMPLIFIER [patent_app_type] => utility [patent_app_number] => 17/465429 [patent_app_country] => US [patent_app_date] => 2021-09-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7203 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17465429 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/465429
Sense amplifier and semiconductor memory device including the sense amplifier Sep 1, 2021 Issued
Array ( [id] => 19093712 [patent_doc_number] => 11955176 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-04-09 [patent_title] => Nonvolatile semiconductor storage device having memory strings and bit lines on opposite sides of the memory strings [patent_app_type] => utility [patent_app_number] => 17/459974 [patent_app_country] => US [patent_app_date] => 2021-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 23161 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 466 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17459974 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/459974
Nonvolatile semiconductor storage device having memory strings and bit lines on opposite sides of the memory strings Aug 26, 2021 Issued
Array ( [id] => 19183573 [patent_doc_number] => 11990169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-05-21 [patent_title] => Transistorless memory cell [patent_app_type] => utility [patent_app_number] => 17/392583 [patent_app_country] => US [patent_app_date] => 2021-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 20 [patent_no_of_words] => 9171 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17392583 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/392583
Transistorless memory cell Aug 2, 2021 Issued
Array ( [id] => 18167450 [patent_doc_number] => 20230034057 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => SYSTEMS AND METHODS FOR INITIALIZING BANDGAP CIRCUITS [patent_app_type] => utility [patent_app_number] => 17/391655 [patent_app_country] => US [patent_app_date] => 2021-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6258 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17391655 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/391655
Systems and methods for initializing bandgap circuits Aug 1, 2021 Issued
Array ( [id] => 17188509 [patent_doc_number] => 20210335394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => MEMORY WITH NON-VOLATILE CONFIGURATIONS FOR EFFICIENT POWER MANAGEMENT AND OPERATION OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/372329 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372329
MEMORY WITH NON-VOLATILE CONFIGURATIONS FOR EFFICIENT POWER MANAGEMENT AND OPERATION OF THE SAME Jul 8, 2021 Pending
Array ( [id] => 17188509 [patent_doc_number] => 20210335394 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-10-28 [patent_title] => MEMORY WITH NON-VOLATILE CONFIGURATIONS FOR EFFICIENT POWER MANAGEMENT AND OPERATION OF THE SAME [patent_app_type] => utility [patent_app_number] => 17/372329 [patent_app_country] => US [patent_app_date] => 2021-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4228 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17372329 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/372329
MEMORY WITH NON-VOLATILE CONFIGURATIONS FOR EFFICIENT POWER MANAGEMENT AND OPERATION OF THE SAME Jul 8, 2021 Pending
Array ( [id] => 18123455 [patent_doc_number] => 20230009065 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => HIGH DENSITY MEMORY WITH REFERENCE CELL AND CORRESPONDING OPERATIONS [patent_app_type] => utility [patent_app_number] => 17/368700 [patent_app_country] => US [patent_app_date] => 2021-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12849 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17368700 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/368700
HIGH DENSITY MEMORY WITH REFERENCE CELL AND CORRESPONDING OPERATIONS Jul 5, 2021 Abandoned
Array ( [id] => 17833369 [patent_doc_number] => 20220270673 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-08-25 [patent_title] => SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS [patent_app_type] => utility [patent_app_number] => 17/365771 [patent_app_country] => US [patent_app_date] => 2021-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17365771 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/365771
SEMICONDUCTOR APPARATUS AND SEMICONDUCTOR MEMORY APPARATUS Jun 30, 2021 Abandoned
Array ( [id] => 17302752 [patent_doc_number] => 20210398591 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-23 [patent_title] => BANK-SELECTIVE POWER EFFICIENT CONTENT-ADDRESSABLE MEMORY [patent_app_type] => utility [patent_app_number] => 17/353803 [patent_app_country] => US [patent_app_date] => 2021-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3157 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17353803 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/353803
Bank-selective power efficient content-addressable memory Jun 20, 2021 Issued
Array ( [id] => 18190436 [patent_doc_number] => 11581037 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-14 [patent_title] => Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column [patent_app_type] => utility [patent_app_number] => 17/341797 [patent_app_country] => US [patent_app_date] => 2021-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11991 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17341797 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/341797
Digital compute-in-memory (DCIM) bit cell circuit layouts and DCIM arrays for multiple operations per column Jun 7, 2021 Issued
Array ( [id] => 20132073 [patent_doc_number] => 12374390 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-29 [patent_title] => SRAM cells with vertical gate-all-round MOSFETs [patent_app_type] => utility [patent_app_number] => 17/340778 [patent_app_country] => US [patent_app_date] => 2021-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 19 [patent_no_of_words] => 962 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 203 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17340778 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/340778
SRAM cells with vertical gate-all-round MOSFETs Jun 6, 2021 Issued
Array ( [id] => 18855629 [patent_doc_number] => 11853207 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Configurable trim settings on a memory device [patent_app_type] => utility [patent_app_number] => 17/336492 [patent_app_country] => US [patent_app_date] => 2021-06-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 5702 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17336492 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/336492
Configurable trim settings on a memory device Jun 1, 2021 Issued
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