Anthan Tran

Array ( [id] => 16240350 [patent_doc_number] => 20200257584 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-08-13 [patent_title] => SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACY [patent_app_type] => utility [patent_app_number] => 16/791674 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5466 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16791674 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16000339 [patent_doc_number] => 20200176040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-04 [patent_title] => SEMICONDUCTOR APPARATUS, SEMICONDUCTOR SYSTEM, AND TRAINING METHOD [patent_app_type] => utility [patent_app_number] => 16/780622 [patent_app_country] => US [patent_app_date] => 2020-02-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4737 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16780622 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18304250 [patent_doc_number] => 11626162 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-04-11 [patent_title] => Partial block memory operations [patent_app_type] => utility [patent_app_number] => 16/744675 [patent_app_country] => US [patent_app_date] => 2020-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 41 [patent_no_of_words] => 19039 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16744675 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15872983 [patent_doc_number] => 20200143895 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-07 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/737467 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16936106 [patent_doc_number] => 20210201995 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-01 [patent_title] => THREE-STATE PROGRAMMING OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/729731 [patent_app_country] => US [patent_app_date] => 2019-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7734 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -25 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16729731 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16447999 [patent_doc_number] => 10839930 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-11-17 [patent_title] => Magnetic domain wall type analog memory element, magnetic domain wall type analog memory, nonvolatile logic circuit, and magnetic neuro-element [patent_app_type] => utility [patent_app_number] => 16/724445 [patent_app_country] => US [patent_app_date] => 2019-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 14091 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 431 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16724445 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16904935 [patent_doc_number] => 20210183851 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-06-17 [patent_title] => APPARATUS WITH VOLTAGE PROTECTION MECHANISM [patent_app_type] => utility [patent_app_number] => 16/712851 [patent_app_country] => US [patent_app_date] => 2019-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5793 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16712851 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17529707 [patent_doc_number] => 11302405 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-12 [patent_title] => System approach to reduce stable threshold voltage (Vt) read disturb degradation [patent_app_type] => utility [patent_app_number] => 16/709749 [patent_app_country] => US [patent_app_date] => 2019-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 12496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 101 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16709749 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16594000 [patent_doc_number] => 10903277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-01-26 [patent_title] => Scalable, stackable, and BEOL-process compatible integrated neuron circuit [patent_app_type] => utility [patent_app_number] => 16/706393 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 23 [patent_no_of_words] => 9744 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 353 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706393 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17270151 [patent_doc_number] => 11195579 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-12-07 [patent_title] => Apparatuses and methods for accessing variable resistance memory device [patent_app_type] => utility [patent_app_number] => 16/706350 [patent_app_country] => US [patent_app_date] => 2019-12-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 7307 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16706350 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16097841 [patent_doc_number] => 20200202907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-06-25 [patent_title] => MULTIPLEXED SIGNAL DEVELOPMENT IN A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/700983 [patent_app_country] => US [patent_app_date] => 2019-12-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 43866 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 65 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16700983 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16180507 [patent_doc_number] => 20200227476 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-16 [patent_title] => RESISTANCE VARIABLE MEMORY [patent_app_type] => utility [patent_app_number] => 16/666421 [patent_app_country] => US [patent_app_date] => 2019-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6809 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16666421 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16637791 [patent_doc_number] => 10916305 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-09 [patent_title] => RRAM-based monotonic counter [patent_app_type] => utility [patent_app_number] => 16/654748 [patent_app_country] => US [patent_app_date] => 2019-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6656 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 64 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16654748 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18857044 [patent_doc_number] => 11854635 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-12-26 [patent_title] => Reclaimable semiconductor device package and associated systems and methods [patent_app_type] => utility [patent_app_number] => 16/653994 [patent_app_country] => US [patent_app_date] => 2019-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5119 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16653994 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17840491 [patent_doc_number] => 20220277797 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-09-01 [patent_title] => AUTHENTICATED SIGNALS FOR WRITE PROTECTION [patent_app_type] => utility [patent_app_number] => 17/633246 [patent_app_country] => US [patent_app_date] => 2019-10-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2956 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 62 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17633246 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16645330 [patent_doc_number] => 10923194 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-16 [patent_title] => Method for erasing memory cells in a flash memory device using a positive well bias voltage and a negative word line voltage [patent_app_type] => utility [patent_app_number] => 16/583352 [patent_app_country] => US [patent_app_date] => 2019-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4048 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16583352 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16722728 [patent_doc_number] => 20210089875 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-03-25 [patent_title] => PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 16/576533 [patent_app_country] => US [patent_app_date] => 2019-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16853 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -46 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16576533 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16300841 [patent_doc_number] => 20200286564 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-09-10 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/569379 [patent_app_country] => US [patent_app_date] => 2019-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9363 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 185 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16569379 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17516646 [patent_doc_number] => 11295806 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-04-05 [patent_title] => Large file integrity techniques [patent_app_type] => utility [patent_app_number] => 16/554247 [patent_app_country] => US [patent_app_date] => 2019-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9017 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16554247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16119253 [patent_doc_number] => 20200211649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-07-02 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF PROCESSING IN MEMORY (PIM) USING THE SAME [patent_app_type] => utility [patent_app_number] => 16/550195 [patent_app_country] => US [patent_app_date] => 2019-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11674 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16550195 [rel_patent_id] =>[rel_patent_doc_number] =>)