
Anthan Tran
Examiner (ID: 4039, Phone: (571)272-8709 , Office: P/2825 )
| Most Active Art Unit | 2825 |
| Art Unit(s) | 2827, 2825 |
| Total Applications | 1098 |
| Issued Applications | 898 |
| Pending Applications | 85 |
| Abandoned Applications | 150 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 14616507
[patent_doc_number] => 10360957
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-23
[patent_title] => Semiconductor device and semiconductor system
[patent_app_type] => utility
[patent_app_number] => 15/713035
[patent_app_country] => US
[patent_app_date] => 2017-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 1
[patent_no_of_words] => 6056
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 156
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15713035
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/713035 | Semiconductor device and semiconductor system | Sep 21, 2017 | Issued |
Array
(
[id] => 15580215
[patent_doc_number] => 10580499
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2020-03-03
[patent_title] => Read only memory
[patent_app_type] => utility
[patent_app_number] => 15/710851
[patent_app_country] => US
[patent_app_date] => 2017-09-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 1
[patent_figures_cnt] => 2
[patent_no_of_words] => 2166
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 206
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710851
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/710851 | Read only memory | Sep 20, 2017 | Issued |
Array
(
[id] => 14091299
[patent_doc_number] => 10241552
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-03-26
[patent_title] => Memory system and control method
[patent_app_type] => utility
[patent_app_number] => 15/710381
[patent_app_country] => US
[patent_app_date] => 2017-09-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 27
[patent_figures_cnt] => 40
[patent_no_of_words] => 17480
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 140
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15710381
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/710381 | Memory system and control method | Sep 19, 2017 | Issued |
Array
(
[id] => 14769741
[patent_doc_number] => 10396276
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-08-27
[patent_title] => Electric-current-generated magnetic field assist type spin-current-induced magnetization reversal element, magnetoresistance effect element, magnetic memory and high-frequency filter
[patent_app_type] => utility
[patent_app_number] => 15/708747
[patent_app_country] => US
[patent_app_date] => 2017-09-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 13306
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 193
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15708747
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/708747 | Electric-current-generated magnetic field assist type spin-current-induced magnetization reversal element, magnetoresistance effect element, magnetic memory and high-frequency filter | Sep 18, 2017 | Issued |
Array
(
[id] => 14558693
[patent_doc_number] => 10347820
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-07-09
[patent_title] => Magnetic memory device
[patent_app_type] => utility
[patent_app_number] => 15/704921
[patent_app_country] => US
[patent_app_date] => 2017-09-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 66
[patent_no_of_words] => 16361
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 280
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15704921
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/704921 | Magnetic memory device | Sep 13, 2017 | Issued |
Array
(
[id] => 14812529
[patent_doc_number] => 20190272874
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-09-05
[patent_title] => MEMORY DEVICE, METHOD OF FORMING THE SAME, METHOD FOR CONTROLLING THE SAME AND MEMORY ARRAY
[patent_app_type] => utility
[patent_app_number] => 16/338033
[patent_app_country] => US
[patent_app_date] => 2017-09-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 13235
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -16
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16338033
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/338033 | MEMORY DEVICE, METHOD OF FORMING THE SAME, METHOD FOR CONTROLLING THE SAME AND MEMORY ARRAY | Sep 11, 2017 | Abandoned |
Array
(
[id] => 12692839
[patent_doc_number] => 20180122779
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-05-03
[patent_title] => STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S
[patent_app_type] => utility
[patent_app_number] => 15/699750
[patent_app_country] => US
[patent_app_date] => 2017-09-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5360
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -18
[patent_words_short_claim] => 149
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15699750
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/699750 | STACKED MEMORY WITH INTERFACE PROVIDING OFFSET Interconnect S | Sep 7, 2017 | Abandoned |
Array
(
[id] => 16738709
[patent_doc_number] => 10964370
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-03-30
[patent_title] => Semiconductor storage element, semiconductor storage device, and semiconductor system
[patent_app_type] => utility
[patent_app_number] => 16/336175
[patent_app_country] => US
[patent_app_date] => 2017-09-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 11184
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 170
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16336175
[rel_patent_id] =>[rel_patent_doc_number] =>) 16/336175 | Semiconductor storage element, semiconductor storage device, and semiconductor system | Sep 6, 2017 | Issued |
Array
(
[id] => 13808159
[patent_doc_number] => 10181348
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-01-15
[patent_title] => Memory device comprising resistance change material and method for driving the same
[patent_app_type] => utility
[patent_app_number] => 15/677055
[patent_app_country] => US
[patent_app_date] => 2017-08-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 19
[patent_figures_cnt] => 24
[patent_no_of_words] => 12033
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 219
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15677055
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/677055 | Memory device comprising resistance change material and method for driving the same | Aug 14, 2017 | Issued |
Array
(
[id] => 13935639
[patent_doc_number] => 20190051335
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-14
[patent_title] => SENSE AMPLIFIER SCHEMES FOR ACCESSING MEMORY CELLS
[patent_app_type] => utility
[patent_app_number] => 15/676721
[patent_app_country] => US
[patent_app_date] => 2017-08-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 31551
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -21
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15676721
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/676721 | Sense amplifier schemes for accessing memory cells | Aug 13, 2017 | Issued |
Array
(
[id] => 12061616
[patent_doc_number] => 20170337960
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-23
[patent_title] => 'SENSE PATH CIRCUITRY SUITABLE FOR MAGNETIC TUNNEL JUNCTION MEMORIES'
[patent_app_type] => utility
[patent_app_number] => 15/673468
[patent_app_country] => US
[patent_app_date] => 2017-08-10
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 5875
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15673468
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/673468 | Sense path circuitry suitable for magnetic tunnel junction memories | Aug 9, 2017 | Issued |
Array
(
[id] => 13112545
[patent_doc_number] => 10074939
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2018-09-11
[patent_title] => Signal isolator having inductive and capacitive signal coupling
[patent_app_type] => utility
[patent_app_number] => 15/671357
[patent_app_country] => US
[patent_app_date] => 2017-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 11
[patent_no_of_words] => 4178
[patent_no_of_claims] => 21
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 159
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671357
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/671357 | Signal isolator having inductive and capacitive signal coupling | Aug 7, 2017 | Issued |
Array
(
[id] => 13030371
[patent_doc_number] => 10037808
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2018-07-31
[patent_title] => Semiconductor device and method for driving semiconductor device
[patent_app_type] => utility
[patent_app_number] => 15/671207
[patent_app_country] => US
[patent_app_date] => 2017-08-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 23
[patent_no_of_words] => 18038
[patent_no_of_claims] => 8
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 157
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15671207
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/671207 | Semiconductor device and method for driving semiconductor device | Aug 7, 2017 | Issued |
Array
(
[id] => 13908797
[patent_doc_number] => 20190043603
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2019-02-07
[patent_title] => Hierarchical Fail Bit Counting Circuit In Memory Device
[patent_app_type] => utility
[patent_app_number] => 15/669739
[patent_app_country] => US
[patent_app_date] => 2017-08-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 11970
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 61
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15669739
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/669739 | Hierarchical fail bit counting circuit in memory device | Aug 3, 2017 | Issued |
Array
(
[id] => 12033776
[patent_doc_number] => 20170323875
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'PACKAGING OF HIGH PERFORMANCE SYSTEM TOPOLOGY FOR NAND MEMORY SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 15/659065
[patent_app_country] => US
[patent_app_date] => 2017-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6934
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659065
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/659065 | Packaging of high performance system topology for NAND memory systems | Jul 24, 2017 | Issued |
Array
(
[id] => 12033777
[patent_doc_number] => 20170323876
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'PACKAGING OF HIGH PERFORMANCE SYSTEM TOPOLOGY FOR NAND MEMORY SYSTEMS'
[patent_app_type] => utility
[patent_app_number] => 15/659083
[patent_app_country] => US
[patent_app_date] => 2017-07-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 21
[patent_no_of_words] => 6934
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15659083
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/659083 | PACKAGING OF HIGH PERFORMANCE SYSTEM TOPOLOGY FOR NAND MEMORY SYSTEMS | Jul 24, 2017 | Abandoned |
Array
(
[id] => 12032741
[patent_doc_number] => 20170322840
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-11-09
[patent_title] => 'SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACY'
[patent_app_type] => utility
[patent_app_number] => 15/658066
[patent_app_country] => US
[patent_app_date] => 2017-07-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 5577
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15658066
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/658066 | Selective reading of memory with improved accuracy | Jul 23, 2017 | Issued |
Array
(
[id] => 14204621
[patent_doc_number] => 10269430
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2019-04-23
[patent_title] => Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells
[patent_app_type] => utility
[patent_app_number] => 15/651985
[patent_app_country] => US
[patent_app_date] => 2017-07-17
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 11
[patent_no_of_words] => 9541
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15651985
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/651985 | Apparatus and methods including a bipolar junction transistor coupled to a string of memory cells | Jul 16, 2017 | Issued |
Array
(
[id] => 11997238
[patent_doc_number] => 20170301393
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-19
[patent_title] => 'SRAM Cells with Vertical Gate-All-Round MOSFETs'
[patent_app_type] => utility
[patent_app_number] => 15/631623
[patent_app_country] => US
[patent_app_date] => 2017-06-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 18
[patent_figures_cnt] => 18
[patent_no_of_words] => 6854
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15631623
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/631623 | SRAM cells with vertical gate-all-round MOSFETs | Jun 22, 2017 | Issued |
Array
(
[id] => 11983376
[patent_doc_number] => 20170287531
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-05
[patent_title] => 'APPARATUSES AND METHODS FOR CONTROLLING DATA TIMING IN A MULTI-MEMORY SYSTEM'
[patent_app_type] => utility
[patent_app_number] => 15/626915
[patent_app_country] => US
[patent_app_date] => 2017-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 8047
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15626915
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/626915 | Apparatuses and methods for controlling data timing in a multi-memory system | Jun 18, 2017 | Issued |