Anthan Tran

Array ( [id] => 12195358 [patent_doc_number] => 09899092 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-02-20 [patent_title] => 'Nonvolatile memory system with program step manager and method for program step management' [patent_app_type] => utility [patent_app_number] => 15/042125 [patent_app_country] => US [patent_app_date] => 2016-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 6523 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15042125 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12293508 [patent_doc_number] => 09934855 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-04-03 [patent_title] => Node retainer circuit incorporating RRAM [patent_app_type] => utility [patent_app_number] => 15/013123 [patent_app_country] => US [patent_app_date] => 2016-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11077 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15013123 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10801113 [patent_doc_number] => 20160147270 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-26 [patent_title] => 'IHS COMPONENT COOLING SYSTEM' [patent_app_type] => utility [patent_app_number] => 15/011008 [patent_app_country] => US [patent_app_date] => 2016-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4590 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15011008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13005601 [patent_doc_number] => 10026471 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-17 [patent_title] => System-on-chip and electronic device having the same [patent_app_type] => utility [patent_app_number] => 15/009149 [patent_app_country] => US [patent_app_date] => 2016-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 11528 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15009149 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12895480 [patent_doc_number] => 20180190335 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => STORAGE DEVICE, MANUFACTURING METHOD THEREFOR, AND STORAGE APPARATUS [patent_app_type] => utility [patent_app_number] => 15/553769 [patent_app_country] => US [patent_app_date] => 2016-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19527 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15553769 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10779797 [patent_doc_number] => 20160125953 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-05 [patent_title] => 'OTP CELL WITH REVERSED MTJ CONNECTION' [patent_app_type] => utility [patent_app_number] => 14/994231 [patent_app_country] => US [patent_app_date] => 2016-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 4448 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14994231 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10771971 [patent_doc_number] => 20160118127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-04-28 [patent_title] => 'NON-VOLATILE SEMICONDUCTOR STORAGE DEVICE' [patent_app_type] => utility [patent_app_number] => 14/990609 [patent_app_country] => US [patent_app_date] => 2016-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6628 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14990609 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13259439 [patent_doc_number] => 10142421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-27 [patent_title] => Methods, systems, and related architectures for managing network connected devices [patent_app_type] => utility [patent_app_number] => 14/984876 [patent_app_country] => US [patent_app_date] => 2015-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 34 [patent_no_of_words] => 17898 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14984876 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13225131 [patent_doc_number] => 10126337 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-11-13 [patent_title] => Microcontroller including power supply monitoring [patent_app_type] => utility [patent_app_number] => 14/982427 [patent_app_country] => US [patent_app_date] => 2015-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14982427 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11717974 [patent_doc_number] => 20170186474 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-29 [patent_title] => 'DUAL-CHANNEL DIMM' [patent_app_type] => utility [patent_app_number] => 14/980709 [patent_app_country] => US [patent_app_date] => 2015-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 10027 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14980709 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10740525 [patent_doc_number] => 20160086676 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-24 [patent_title] => 'METHOD AND SYSTEM FOR IMPROVING THE RADIATION TOLERANCE OF FLOATING GATE MEMORIES' [patent_app_type] => utility [patent_app_number] => 14/958202 [patent_app_country] => US [patent_app_date] => 2015-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7234 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958202 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13527883 [patent_doc_number] => 20180315484 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-01 [patent_title] => A METHOD FOR OPERATING A SEMICONDUCTOR MEMORY [patent_app_type] => utility [patent_app_number] => 15/769619 [patent_app_country] => US [patent_app_date] => 2015-11-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15769619 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10794883 [patent_doc_number] => 20160141040 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-05-19 [patent_title] => 'METHOD FOR ERASING MEMORY CELLS IN A FLASH MEMORY DEVICE USING A POSITIVE WELL BIAS VOLTAGE AND A NEGATIVE WORD LINE VOLTAGE' [patent_app_type] => utility [patent_app_number] => 14/933264 [patent_app_country] => US [patent_app_date] => 2015-11-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4325 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14933264 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11904098 [patent_doc_number] => 09773537 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-09-26 [patent_title] => 'Sense path circuitry suitable for magnetic tunnel junction memories' [patent_app_type] => utility [patent_app_number] => 14/924269 [patent_app_country] => US [patent_app_date] => 2015-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5874 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 214 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14924269 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11592615 [patent_doc_number] => 20170117027 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'TOP PINNED SOT-MRAM ARCHITECTURE WITH IN-STACK SELECTOR' [patent_app_type] => utility [patent_app_number] => 14/919247 [patent_app_country] => US [patent_app_date] => 2015-10-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3074 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14919247 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10696652 [patent_doc_number] => 20160042800 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-02-11 [patent_title] => 'SEMICONDUCTOR MEMORY DEVICE' [patent_app_type] => utility [patent_app_number] => 14/918036 [patent_app_country] => US [patent_app_date] => 2015-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 8873 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14918036 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11802103 [patent_doc_number] => 09542993 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Leakage-current abatement circuitry for memory arrays' [patent_app_type] => utility [patent_app_number] => 14/887210 [patent_app_country] => US [patent_app_date] => 2015-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3733 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14887210 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11339371 [patent_doc_number] => 20160365127 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-12-15 [patent_title] => 'MEMORY SYSTEM AND OPERATING METHOD THEREOF' [patent_app_type] => utility [patent_app_number] => 14/884411 [patent_app_country] => US [patent_app_date] => 2015-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6107 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14884411 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15397555 [patent_doc_number] => 10539429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-01-21 [patent_title] => Accelerometer-based systems and methods and quantifying steps [patent_app_type] => utility [patent_app_number] => 14/879718 [patent_app_country] => US [patent_app_date] => 2015-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 7221 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 349 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14879718 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 12147397 [patent_doc_number] => 09881654 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-01-30 [patent_title] => 'Power source for memory circuitry' [patent_app_type] => utility [patent_app_number] => 14/877723 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 5341 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877723 [rel_patent_id] =>[rel_patent_doc_number] =>)