Search

Anthan Tran

Examiner (ID: 6921, Phone: (571)272-8709 , Office: P/2825 )

Most Active Art Unit
2825
Art Unit(s)
2827, 2825
Total Applications
1101
Issued Applications
902
Pending Applications
79
Abandoned Applications
150

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 18407507 [patent_doc_number] => 20230168860 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-01 [patent_title] => MAGNETIC PROCESSING UNIT [patent_app_type] => utility [patent_app_number] => 18/162391 [patent_app_country] => US [patent_app_date] => 2023-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16017 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18162391 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/162391
Magnetic processing unit Jan 30, 2023 Issued
Array ( [id] => 19980009 [patent_doc_number] => 12347495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 18/095306 [patent_app_country] => US [patent_app_date] => 2023-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 14 [patent_no_of_words] => 3673 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18095306 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/095306
Memory device Jan 9, 2023 Issued
Array ( [id] => 19507612 [patent_doc_number] => 12119041 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-10-15 [patent_title] => Signal synchronization adjustment method and signal synchronization adjustment circuit [patent_app_type] => utility [patent_app_number] => 18/093817 [patent_app_country] => US [patent_app_date] => 2023-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 9756 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18093817 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/093817
Signal synchronization adjustment method and signal synchronization adjustment circuit Jan 5, 2023 Issued
Array ( [id] => 20305189 [patent_doc_number] => 12451185 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-10-21 [patent_title] => Method for storing information in a coded manner in non-volatile memory cells, decoding method and non-volatile memory [patent_app_type] => utility [patent_app_number] => 18/148378 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 5644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18148378 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/148378
Method for storing information in a coded manner in non-volatile memory cells, decoding method and non-volatile memory Dec 28, 2022 Issued
Array ( [id] => 19175866 [patent_doc_number] => 20240161840 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-16 [patent_title] => INTERFACE PROTOCOLS BETWEEN MEMORY CONTROLLER AND NAND FLASH MEMORY FOR CACHE PROGRAMMING [patent_app_type] => utility [patent_app_number] => 18/091020 [patent_app_country] => US [patent_app_date] => 2022-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 25222 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18091020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/091020
Interface protocols between memory controller and NAND flash memory for cache programming Dec 28, 2022 Issued
Array ( [id] => 19252495 [patent_doc_number] => 20240203492 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-06-20 [patent_title] => MEMORY DEVICE AND OPERATING METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/090303 [patent_app_country] => US [patent_app_date] => 2022-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16987 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18090303 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/090303
Memory device and operating method thereof Dec 27, 2022 Issued
Array ( [id] => 19634329 [patent_doc_number] => 20240412778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-12 [patent_title] => MEMORY CELL, ARRAY READ-WRITE METHOD, CONTROL CHIP, MEMORY, AND ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/700634 [patent_app_country] => US [patent_app_date] => 2022-12-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15097 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18700634 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/700634
MEMORY CELL, ARRAY READ-WRITE METHOD, CONTROL CHIP, MEMORY, AND ELECTRONIC DEVICE Dec 20, 2022 Pending
Array ( [id] => 18312085 [patent_doc_number] => 20230115985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-04-13 [patent_title] => MERGED BUFFER AND MEMORY DEVICE INCLUDING THE MERGED BUFFER [patent_app_type] => utility [patent_app_number] => 18/078732 [patent_app_country] => US [patent_app_date] => 2022-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12513 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18078732 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/078732
Merged buffer and memory device including the merged buffer Dec 8, 2022 Issued
Array ( [id] => 18194931 [patent_doc_number] => 20230048450 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => Drift Aware Read Operations [patent_app_type] => utility [patent_app_number] => 17/980382 [patent_app_country] => US [patent_app_date] => 2022-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11548 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17980382 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/980382
Drift aware read operations Nov 2, 2022 Issued
Array ( [id] => 19596780 [patent_doc_number] => 12154633 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-11-26 [patent_title] => Input/output pad suitable for memory and method of controlling same [patent_app_type] => utility [patent_app_number] => 18/046995 [patent_app_country] => US [patent_app_date] => 2022-10-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5113 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18046995 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/046995
Input/output pad suitable for memory and method of controlling same Oct 16, 2022 Issued
Array ( [id] => 19427957 [patent_doc_number] => 12087385 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2024-09-10 [patent_title] => Method for obtaining circuit noise parameters and electronic device [patent_app_type] => utility [patent_app_number] => 17/953297 [patent_app_country] => US [patent_app_date] => 2022-09-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 8398 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 308 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17953297 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/953297
Method for obtaining circuit noise parameters and electronic device Sep 25, 2022 Issued
Array ( [id] => 18144875 [patent_doc_number] => 20230018727 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => SRAM ARCHITECTURE [patent_app_type] => utility [patent_app_number] => 17/933933 [patent_app_country] => US [patent_app_date] => 2022-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7215 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 345 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17933933 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/933933
SRAM architecture Sep 20, 2022 Issued
Array ( [id] => 18284647 [patent_doc_number] => 20230100119 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-30 [patent_title] => OPERATING METHOD OF STORAGE DEVICE, OPERATING METHOD OF HOST, AND STORAGE SYSTEM INCLUDING THE STORAGE DEVICE AND THE HOST [patent_app_type] => utility [patent_app_number] => 17/948858 [patent_app_country] => US [patent_app_date] => 2022-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18390 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17948858 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/948858
Operating method of storage device, operating method of host, and storage system including the storage device and the host Sep 19, 2022 Issued
Array ( [id] => 18192715 [patent_doc_number] => 20230046234 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-16 [patent_title] => SEMICONDUCTOR SYSTEM AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 17/942874 [patent_app_country] => US [patent_app_date] => 2022-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10120 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17942874 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/942874
Semiconductor system and method of operating the same Sep 11, 2022 Issued
Array ( [id] => 18112645 [patent_doc_number] => 20230005525 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-05 [patent_title] => APPARATUSES AND METHODS FOR GENERATING REFRESH ADDRESSES [patent_app_type] => utility [patent_app_number] => 17/929981 [patent_app_country] => US [patent_app_date] => 2022-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11600 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17929981 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/929981
Apparatuses and methods for generating refresh addresses Sep 5, 2022 Issued
Array ( [id] => 19886696 [patent_doc_number] => 12272421 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-04-08 [patent_title] => Creating dynamic latches above a three-dimensional non-volatile memory array [patent_app_type] => utility [patent_app_number] => 17/895959 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 14696 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895959 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895959
Creating dynamic latches above a three-dimensional non-volatile memory array Aug 24, 2022 Issued
Array ( [id] => 19007453 [patent_doc_number] => 20240071524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => HYBRID SMART VERIFY FOR QLC/TLC DIE [patent_app_type] => utility [patent_app_number] => 17/895412 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895412 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/895412
Hybrid smart verify for QLC/TLC die Aug 24, 2022 Issued
Array ( [id] => 19007436 [patent_doc_number] => 20240071507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/894248 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894248 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/894248
Memory for programming data states of memory cells Aug 23, 2022 Issued
Array ( [id] => 18061412 [patent_doc_number] => 20220392498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => PEAK CURRENT REDUCTION USING DYNAMIC CLOCKING DURING CHARGE PUMP RECOVERY PERIOD [patent_app_type] => utility [patent_app_number] => 17/890047 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890047 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/890047
Peak current reduction using dynamic clocking during charge pump recovery period Aug 16, 2022 Issued
Array ( [id] => 19356703 [patent_doc_number] => 12057158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-06 [patent_title] => Method for operating dynamic memory [patent_app_type] => utility [patent_app_number] => 18/021177 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6129 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18021177 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/021177
Method for operating dynamic memory Aug 11, 2022 Issued
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