Anthan Tran

Array ( [id] => 19007453 [patent_doc_number] => 20240071524 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => HYBRID SMART VERIFY FOR QLC/TLC DIE [patent_app_type] => utility [patent_app_number] => 17/895412 [patent_app_country] => US [patent_app_date] => 2022-08-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17895412 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19007436 [patent_doc_number] => 20240071507 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-29 [patent_title] => APPARATUS AND METHODS FOR PROGRAMMING DATA STATES OF MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 17/894248 [patent_app_country] => US [patent_app_date] => 2022-08-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 22801 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17894248 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18061412 [patent_doc_number] => 20220392498 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-08 [patent_title] => PEAK CURRENT REDUCTION USING DYNAMIC CLOCKING DURING CHARGE PUMP RECOVERY PERIOD [patent_app_type] => utility [patent_app_number] => 17/890047 [patent_app_country] => US [patent_app_date] => 2022-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9624 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17890047 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19356703 [patent_doc_number] => 12057158 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2024-08-06 [patent_title] => Method for operating dynamic memory [patent_app_type] => utility [patent_app_number] => 18/021177 [patent_app_country] => US [patent_app_date] => 2022-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6129 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 354 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18021177 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18039716 [patent_doc_number] => 20220383933 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => RESERVED ROWS FOR ROW-COPY OPERATIONS FOR SEMICONDUCTOR MEMORY DEVICES AND ASSOCIATED METHODS AND SYSTEMS [patent_app_type] => utility [patent_app_number] => 17/885467 [patent_app_country] => US [patent_app_date] => 2022-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10625 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17885467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18227584 [patent_doc_number] => 20230066578 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-03-02 [patent_title] => SENSE AMPLIFICATION CIRCUIT AND METHOD OF READING OUT DATA [patent_app_type] => utility [patent_app_number] => 17/818110 [patent_app_country] => US [patent_app_date] => 2022-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9442 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 424 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17818110 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18038870 [patent_doc_number] => 20220383086 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-12-01 [patent_title] => PRECISION TUNING FOR THE PROGRAMMING OF ANALOG NEURAL MEMORY IN A DEEP LEARNING ARTIFICIAL NEURAL NETWORK [patent_app_type] => utility [patent_app_number] => 17/875167 [patent_app_country] => US [patent_app_date] => 2022-07-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 16882 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17875167 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18721578 [patent_doc_number] => 11798935 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-10-24 [patent_title] => Apparatus with voltage protection mechanism [patent_app_type] => utility [patent_app_number] => 17/871681 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5824 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 287 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871681 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18219331 [patent_doc_number] => 11594277 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-02-28 [patent_title] => Neural network computation method using adaptive data representation [patent_app_type] => utility [patent_app_number] => 17/871811 [patent_app_country] => US [patent_app_date] => 2022-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 5348 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17871811 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18905747 [patent_doc_number] => 20240021232 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => Systems, Devices, and Methods of Cache Memory [patent_app_type] => utility [patent_app_number] => 17/866448 [patent_app_country] => US [patent_app_date] => 2022-07-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9895 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17866448 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18905758 [patent_doc_number] => 20240021243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-18 [patent_title] => SENSE CIRCUIT AND HIGH-SPEED MEMORY STRUCTURE INCORPORATING THE SENSE CIRCIUT [patent_app_type] => utility [patent_app_number] => 17/812485 [patent_app_country] => US [patent_app_date] => 2022-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11812 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17812485 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18124310 [patent_doc_number] => 20230009922 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => Decoupled Execution Of Workload For Crossbar Arrays [patent_app_type] => utility [patent_app_number] => 17/860419 [patent_app_country] => US [patent_app_date] => 2022-07-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2116 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -12 [patent_words_short_claim] => 48 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17860419 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19765701 [patent_doc_number] => 12223999 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-02-11 [patent_title] => Synchronous input buffer control using a write shifter [patent_app_type] => utility [patent_app_number] => 17/853517 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 7198 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 77 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18144315 [patent_doc_number] => 20230018166 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-19 [patent_title] => READ AND PROGRAMMING DECODING SYSTEM FOR ANALOG NEURAL MEMORY [patent_app_type] => utility [patent_app_number] => 17/853315 [patent_app_country] => US [patent_app_date] => 2022-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14798 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17853315 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848484 [patent_doc_number] => 20230410888 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => INPUT BUFFER BIAS CURRENT CONTROL [patent_app_type] => utility [patent_app_number] => 17/845640 [patent_app_country] => US [patent_app_date] => 2022-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5750 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17845640 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17915688 [patent_doc_number] => 20220318084 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-10-06 [patent_title] => SELECTIVE READING OF MEMORY WITH IMPROVED ACCURACY [patent_app_type] => utility [patent_app_number] => 17/843237 [patent_app_country] => US [patent_app_date] => 2022-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17843237 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848481 [patent_doc_number] => 20230410885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => APPARATUSES AND METHODS FOR CONTROLLING SENSE AMPLIFIER OPERATION [patent_app_type] => utility [patent_app_number] => 17/841517 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6371 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841517 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848508 [patent_doc_number] => 20230410912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DIE BY DIE TRIMMING OF DRAIN-SIDE SELECT GATE THRESHOLD VOLTAGE TO REDUCE CUMULATIVE READ DISTURB [patent_app_type] => utility [patent_app_number] => 17/841160 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841160 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19720099 [patent_doc_number] => 12205642 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-21 [patent_title] => Memory device [patent_app_type] => utility [patent_app_number] => 17/841287 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 9355 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 800 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841287 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18848508 [patent_doc_number] => 20230410912 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-21 [patent_title] => DIE BY DIE TRIMMING OF DRAIN-SIDE SELECT GATE THRESHOLD VOLTAGE TO REDUCE CUMULATIVE READ DISTURB [patent_app_type] => utility [patent_app_number] => 17/841160 [patent_app_country] => US [patent_app_date] => 2022-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14205 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17841160 [rel_patent_id] =>[rel_patent_doc_number] =>)