Application number | Title of the application | Filing Date | Status |
---|
Array
(
[id] => 6555039
[patent_doc_number] => 20020194467
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2002-12-19
[patent_title] => 'Hardware efficient handling of instruction exceptions to limit adverse impact on performance'
[patent_app_type] => new
[patent_app_number] => 09/884675
[patent_app_country] => US
[patent_app_date] => 2001-06-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 2
[patent_no_of_words] => 3864
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 28
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] => publications/A1/0194/20020194467.pdf
[firstpage_image] =>[orig_patent_app_number] => 09884675
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/884675 | Method and system with multiple exception handlers in a processor | Jun 18, 2001 | Issued |
Array
(
[id] => 1166233
[patent_doc_number] => 06772321
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-03
[patent_title] => 'Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor'
[patent_app_type] => B2
[patent_app_number] => 09/761360
[patent_app_country] => US
[patent_app_date] => 2001-01-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 8
[patent_no_of_words] => 4585
[patent_no_of_claims] => 27
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 201
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/772/06772321.pdf
[firstpage_image] =>[orig_patent_app_number] => 09761360
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/761360 | Method and apparatus for using an assist processor and value speculation to facilitate prefetching for a primary processor | Jan 15, 2001 | Issued |
Array
(
[id] => 1033761
[patent_doc_number] => 06880073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-04-12
[patent_title] => 'Speculative execution of instructions and processes before completion of preceding barrier operations'
[patent_app_type] => utility
[patent_app_number] => 09/753053
[patent_app_country] => US
[patent_app_date] => 2000-12-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6718
[patent_no_of_claims] => 26
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 94
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/880/06880073.pdf
[firstpage_image] =>[orig_patent_app_number] => 09753053
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/753053 | Speculative execution of instructions and processes before completion of preceding barrier operations | Dec 27, 2000 | Issued |
Array
(
[id] => 987735
[patent_doc_number] => 06925549
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2005-08-02
[patent_title] => 'Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages'
[patent_app_type] => utility
[patent_app_number] => 09/746647
[patent_app_country] => US
[patent_app_date] => 2000-12-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4140
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 248
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/925/06925549.pdf
[firstpage_image] =>[orig_patent_app_number] => 09746647
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/746647 | Asynchronous pipeline control interface using tag values to control passing data through successive pipeline stages | Dec 20, 2000 | Issued |
Array
(
[id] => 1155305
[patent_doc_number] => 06779108
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2004-08-17
[patent_title] => 'Incorporating trigger loads in branch histories for branch prediction'
[patent_app_type] => B2
[patent_app_number] => 09/738115
[patent_app_country] => US
[patent_app_date] => 2000-12-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 2616
[patent_no_of_claims] => 37
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 56
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/779/06779108.pdf
[firstpage_image] =>[orig_patent_app_number] => 09738115
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/738115 | Incorporating trigger loads in branch histories for branch prediction | Dec 14, 2000 | Issued |
09/530959 | COMPUTER SYSTEM | Jul 5, 2000 | Abandoned |
Array
(
[id] => 1017243
[patent_doc_number] => 06895495
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-05-17
[patent_title] => 'Next available buffer allocation circuit'
[patent_app_type] => utility
[patent_app_number] => 09/607783
[patent_app_country] => US
[patent_app_date] => 2000-06-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 1583
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/895/06895495.pdf
[firstpage_image] =>[orig_patent_app_number] => 09607783
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/607783 | Next available buffer allocation circuit | Jun 29, 2000 | Issued |
Array
(
[id] => 1083015
[patent_doc_number] => 06836841
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-12-28
[patent_title] => 'Predicting output of a reuse region using prior execution results associated with the reuse region'
[patent_app_type] => B1
[patent_app_number] => 09/607580
[patent_app_country] => US
[patent_app_date] => 2000-06-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 10
[patent_no_of_words] => 6945
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 84
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/836/06836841.pdf
[firstpage_image] =>[orig_patent_app_number] => 09607580
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/607580 | Predicting output of a reuse region using prior execution results associated with the reuse region | Jun 28, 2000 | Issued |
Array
(
[id] => 1179157
[patent_doc_number] => 06757811
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-29
[patent_title] => 'Slack fetch to improve performance in a simultaneous and redundantly threaded processor'
[patent_app_type] => B1
[patent_app_number] => 09/584034
[patent_app_country] => US
[patent_app_date] => 2000-05-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 2
[patent_figures_cnt] => 3
[patent_no_of_words] => 4422
[patent_no_of_claims] => 25
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/757/06757811.pdf
[firstpage_image] =>[orig_patent_app_number] => 09584034
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/584034 | Slack fetch to improve performance in a simultaneous and redundantly threaded processor | May 29, 2000 | Issued |
Array
(
[id] => 1206932
[patent_doc_number] => 06721877
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-13
[patent_title] => 'Branch predictor that selects between predictions based on stored prediction selector and branch predictor index generation'
[patent_app_type] => B1
[patent_app_number] => 09/579245
[patent_app_country] => US
[patent_app_date] => 2000-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 14985
[patent_no_of_claims] => 18
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 91
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/721/06721877.pdf
[firstpage_image] =>[orig_patent_app_number] => 09579245
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/579245 | Branch predictor that selects between predictions based on stored prediction selector and branch predictor index generation | May 24, 2000 | Issued |
Array
(
[id] => 1206930
[patent_doc_number] => 06721876
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-04-13
[patent_title] => 'Branch predictor index generation using varied bit positions or bit order reversal'
[patent_app_type] => B1
[patent_app_number] => 09/578954
[patent_app_country] => US
[patent_app_date] => 2000-05-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 9
[patent_figures_cnt] => 9
[patent_no_of_words] => 14970
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/721/06721876.pdf
[firstpage_image] =>[orig_patent_app_number] => 09578954
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/578954 | Branch predictor index generation using varied bit positions or bit order reversal | May 24, 2000 | Issued |
Array
(
[id] => 1236349
[patent_doc_number] => 06694425
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-17
[patent_title] => 'Selective flush of shared and other pipeline stages in a multithread processor'
[patent_app_type] => B1
[patent_app_number] => 09/564930
[patent_app_country] => US
[patent_app_date] => 2000-05-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 7767
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 128
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/694/06694425.pdf
[firstpage_image] =>[orig_patent_app_number] => 09564930
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/564930 | Selective flush of shared and other pipeline stages in a multithread processor | May 3, 2000 | Issued |
Array
(
[id] => 1004685
[patent_doc_number] => 06910124
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2005-06-21
[patent_title] => 'Apparatus and method for recovering a link stack from mis-speculation'
[patent_app_type] => utility
[patent_app_number] => 09/562161
[patent_app_country] => US
[patent_app_date] => 2000-05-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 6638
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 59
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/910/06910124.pdf
[firstpage_image] =>[orig_patent_app_number] => 09562161
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562161 | Apparatus and method for recovering a link stack from mis-speculation | May 1, 2000 | Issued |
Array
(
[id] => 1298158
[patent_doc_number] => 06631460
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-10-07
[patent_title] => 'Advanced load address table entry invalidation based on register address wraparound'
[patent_app_type] => B1
[patent_app_number] => 09/559508
[patent_app_country] => US
[patent_app_date] => 2000-04-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 10
[patent_no_of_words] => 12195
[patent_no_of_claims] => 32
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 46
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/631/06631460.pdf
[firstpage_image] =>[orig_patent_app_number] => 09559508
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/559508 | Advanced load address table entry invalidation based on register address wraparound | Apr 26, 2000 | Issued |
09/561378 | Method and apparatus to reduce context switching time in a multiprocessing environment | Apr 26, 2000 | Abandoned |
Array
(
[id] => 1234342
[patent_doc_number] => 06697933
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-02-24
[patent_title] => 'Method and apparatus for fast, speculative floating point register renaming'
[patent_app_type] => B1
[patent_app_number] => 09/539221
[patent_app_country] => US
[patent_app_date] => 2000-03-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 7
[patent_no_of_words] => 4211
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 77
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/697/06697933.pdf
[firstpage_image] =>[orig_patent_app_number] => 09539221
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/539221 | Method and apparatus for fast, speculative floating point register renaming | Mar 29, 2000 | Issued |
Array
(
[id] => 1181218
[patent_doc_number] => 06754813
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-06-22
[patent_title] => 'Apparatus and method of processing information for suppression of branch prediction'
[patent_app_type] => B1
[patent_app_number] => 09/531608
[patent_app_country] => US
[patent_app_date] => 2000-03-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 20
[patent_figures_cnt] => 20
[patent_no_of_words] => 9177
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 6
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/754/06754813.pdf
[firstpage_image] =>[orig_patent_app_number] => 09531608
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/531608 | Apparatus and method of processing information for suppression of branch prediction | Mar 20, 2000 | Issued |
09/524214 | Device and method for eliminating redundant stack operations | Mar 12, 2000 | Abandoned |
Array
(
[id] => 1284662
[patent_doc_number] => 06651163
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Exception handling with reduced overhead in a multithreaded multiprocessing system'
[patent_app_type] => B1
[patent_app_number] => 09/521248
[patent_app_country] => US
[patent_app_date] => 2000-03-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 15
[patent_figures_cnt] => 16
[patent_no_of_words] => 15648
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 147
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/651/06651163.pdf
[firstpage_image] =>[orig_patent_app_number] => 09521248
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/521248 | Exception handling with reduced overhead in a multithreaded multiprocessing system | Mar 7, 2000 | Issued |
Array
(
[id] => 1116639
[patent_doc_number] => 06804769
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2004-10-12
[patent_title] => 'Unified buffer for tracking disparate long-latency operations in a microprocessor'
[patent_app_type] => B1
[patent_app_number] => 09/507036
[patent_app_country] => US
[patent_app_date] => 2000-02-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 3
[patent_no_of_words] => 2759
[patent_no_of_claims] => 34
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 104
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/06/804/06804769.pdf
[firstpage_image] =>[orig_patent_app_number] => 09507036
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/507036 | Unified buffer for tracking disparate long-latency operations in a microprocessor | Feb 17, 2000 | Issued |