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Anthony Chi

Examiner (ID: 19757)

Most Active Art Unit
2204
Art Unit(s)
3641, 2204
Total Applications
318
Issued Applications
283
Pending Applications
13
Abandoned Applications
22

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20347721 [patent_doc_number] => 12471460 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-11 [patent_title] => Display apparatus including a pad at a non-display area overlapping with a conductor connecting a conductive line to the pad [patent_app_type] => utility [patent_app_number] => 17/879590 [patent_app_country] => US [patent_app_date] => 2022-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10496 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17879590 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/879590
Display apparatus including a pad at a non-display area overlapping with a conductor connecting a conductive line to the pad Aug 1, 2022 Issued
Array ( [id] => 18498825 [patent_doc_number] => 20230221552 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-07-13 [patent_title] => DISPLAY DEVICE, AUGMENTED REALITY DEVICE INCLUDING DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 17/877402 [patent_app_country] => US [patent_app_date] => 2022-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12872 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17877402 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/877402
DISPLAY DEVICE, AUGMENTED REALITY DEVICE INCLUDING DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY DEVICE Jul 28, 2022 Pending
Array ( [id] => 18900462 [patent_doc_number] => 20240015947 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE HAVING BURIED GATE STRUCTURE [patent_app_type] => utility [patent_app_number] => 17/861743 [patent_app_country] => US [patent_app_date] => 2022-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8642 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17861743 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/861743
Method for manufacturing semiconductor device having buried gate structure Jul 10, 2022 Issued
Array ( [id] => 18166435 [patent_doc_number] => 20230033038 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-02 [patent_title] => TWO-DIMENSION SELF-ALIGNED SCHEME WITH SUBTRACTIVE METAL ETCH [patent_app_type] => utility [patent_app_number] => 17/859838 [patent_app_country] => US [patent_app_date] => 2022-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7645 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17859838 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/859838
Two-dimension self-aligned scheme with subtractive metal etch Jul 6, 2022 Issued
Array ( [id] => 18124051 [patent_doc_number] => 20230009662 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-01-12 [patent_title] => NITRIDE SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 17/858168 [patent_app_country] => US [patent_app_date] => 2022-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12604 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17858168 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/858168
Nitride semiconductor device Jul 5, 2022 Issued
Array ( [id] => 18900475 [patent_doc_number] => 20240015960 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP METAL PLATES FOR BACKSIDE VIA STRUCTURES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/857375 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 117 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857375 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857375
Three-dimensional memory device containing etch stop metal plates for backside via structures and methods for forming the same Jul 4, 2022 Issued
Array ( [id] => 18900474 [patent_doc_number] => 20240015959 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-11 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE CONTAINING ETCH STOP METAL PLATES FOR BACKSIDE VIA STRUCTURES AND METHODS FOR FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/857335 [patent_app_country] => US [patent_app_date] => 2022-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 28994 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17857335 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/857335
Three-dimensional memory device containing etch stop metal plates for backside via structures and methods for forming the same Jul 4, 2022 Issued
Array ( [id] => 18882941 [patent_doc_number] => 20240006310 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => THREE-DIMENSIONAL MEMORY DEVICE WITH HIGH CONTACT VIA DENSITY AND METHODS OF FORMING THE SAME [patent_app_type] => utility [patent_app_number] => 17/810124 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18788 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810124 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810124
Three-dimensional memory device with high contact via density and methods of forming the same Jun 29, 2022 Issued
Array ( [id] => 19980006 [patent_doc_number] => 12347492 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-01 [patent_title] => Three-dimensional memory device with high contact via density and methods of forming the same [patent_app_type] => utility [patent_app_number] => 17/810097 [patent_app_country] => US [patent_app_date] => 2022-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 70 [patent_figures_cnt] => 97 [patent_no_of_words] => 14344 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17810097 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/810097
Three-dimensional memory device with high contact via density and methods of forming the same Jun 29, 2022 Issued
Array ( [id] => 18865916 [patent_doc_number] => 20230420353 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-12-28 [patent_title] => ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES [patent_app_type] => utility [patent_app_number] => 17/848053 [patent_app_country] => US [patent_app_date] => 2022-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11422 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 113 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17848053 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/848053
ASYMMETRICAL DIELECTRIC-TO-METAL ADHESION ARCHITECTURE FOR ELECTRONIC PACKAGES Jun 22, 2022 Pending
Array ( [id] => 20597953 [patent_doc_number] => 12581690 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-17 [patent_title] => Method of forming semiconductor device with implanted nanosheets [patent_app_type] => utility [patent_app_number] => 17/842060 [patent_app_country] => US [patent_app_date] => 2022-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 44 [patent_no_of_words] => 4572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17842060 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/842060
Method of forming semiconductor device with implanted nanosheets Jun 15, 2022 Issued
Array ( [id] => 18656593 [patent_doc_number] => 20230302494 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-28 [patent_title] => HYBRID ULTRASONIC TRANSDUCER SYSTEM [patent_app_type] => utility [patent_app_number] => 17/832937 [patent_app_country] => US [patent_app_date] => 2022-06-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17920 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17832937 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/832937
Hybrid ultrasonic transducer system Jun 5, 2022 Issued
Array ( [id] => 18213583 [patent_doc_number] => 20230059848 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-02-23 [patent_title] => THROUGH WAFER TRENCH ISOLATION [patent_app_type] => utility [patent_app_number] => 17/828356 [patent_app_country] => US [patent_app_date] => 2022-05-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9996 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17828356 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/828356
THROUGH WAFER TRENCH ISOLATION May 30, 2022 Pending
Array ( [id] => 19437930 [patent_doc_number] => 20240306428 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-12 [patent_title] => Display Substrate, Manufacturing Method Thereof and Display Device [patent_app_type] => utility [patent_app_number] => 18/028265 [patent_app_country] => US [patent_app_date] => 2022-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 15730 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18028265 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/028265
Display Substrate, Manufacturing Method Thereof and Display Device Apr 23, 2022 Pending
Array ( [id] => 18712952 [patent_doc_number] => 20230335585 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-10-19 [patent_title] => STACKED FIELD-EFFECT TRANSISTORS HAVING LATCH CROSS-COUPLING CONNECTIONS [patent_app_type] => utility [patent_app_number] => 17/722376 [patent_app_country] => US [patent_app_date] => 2022-04-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6538 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17722376 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/722376
STACKED FIELD-EFFECT TRANSISTORS HAVING LATCH CROSS-COUPLING CONNECTIONS Apr 16, 2022 Pending
Array ( [id] => 18653295 [patent_doc_number] => 20230299135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-09-21 [patent_title] => PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT [patent_app_type] => utility [patent_app_number] => 17/697129 [patent_app_country] => US [patent_app_date] => 2022-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11673 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17697129 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/697129
PARTIAL GATE CUT STRUCTURES IN AN INTEGRATED CIRCUIT Mar 16, 2022 Pending
Array ( [id] => 20375298 [patent_doc_number] => 12482742 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-11-25 [patent_title] => Enhanced linerless vias [patent_app_type] => utility [patent_app_number] => 17/646572 [patent_app_country] => US [patent_app_date] => 2021-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 12 [patent_no_of_words] => 0 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17646572 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/646572
Enhanced linerless vias Dec 29, 2021 Issued
Array ( [id] => 18473275 [patent_doc_number] => 20230207563 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-06-29 [patent_title] => GATE ALL AROUND COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS [patent_app_type] => utility [patent_app_number] => 17/565367 [patent_app_country] => US [patent_app_date] => 2021-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3965 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 58 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17565367 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/565367
GATE ALL AROUND COMPLEMENTARY METAL-OXIDE-SEMICONDUCTOR FIELD EFFECT TRANSISTORS Dec 28, 2021 Pending
Array ( [id] => 19054968 [patent_doc_number] => 20240096937 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-21 [patent_title] => POWER SEMICONDUCTOR DEVICE AND A METHOD FOR PRODUCING A POWER SEMICONDUCTOR DEVICE [patent_app_type] => utility [patent_app_number] => 18/039920 [patent_app_country] => US [patent_app_date] => 2021-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5099 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18039920 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/039920
Power semiconductor device and a method for producing a power semiconductor device Nov 30, 2021 Issued
Array ( [id] => 19288290 [patent_doc_number] => 20240224773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-07-04 [patent_title] => DISPLAY DEVICES AND DISPLAY PANELS THEREOF [patent_app_type] => utility [patent_app_number] => 17/922479 [patent_app_country] => US [patent_app_date] => 2021-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5039 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 40 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17922479 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/922479
Display devices and display panels thereof Oct 25, 2021 Issued
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