Search

Anthony Ho

Examiner (ID: 7082, Phone: (571)270-1432 , Office: P/2817 )

Most Active Art Unit
2817
Art Unit(s)
2817, 2809, 2815
Total Applications
2093
Issued Applications
1841
Pending Applications
122
Abandoned Applications
159

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20096099 [patent_doc_number] => 20250226035 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ERASE DISTRIBUTION TIGHTENING TO IMPROVE READ BUDGET WINDOW IN A MEMORY SUB-SYSTEM [patent_app_type] => utility [patent_app_number] => 18/977030 [patent_app_country] => US [patent_app_date] => 2024-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5498 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18977030 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/977030
ERASE DISTRIBUTION TIGHTENING TO IMPROVE READ BUDGET WINDOW IN A MEMORY SUB-SYSTEM Dec 10, 2024 Pending
Array ( [id] => 20090987 [patent_doc_number] => 20250220923 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => MEMORY CIRCUIT, RESISTIVE NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/974692 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8014 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18974692 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/974692
MEMORY CIRCUIT, RESISTIVE NON-VOLATILE MEMORY AND OPERATION METHOD THEREOF Dec 8, 2024 Pending
Array ( [id] => 20167639 [patent_doc_number] => 20250259686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-08-14 [patent_title] => PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 18/973603 [patent_app_country] => US [patent_app_date] => 2024-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14254 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18973603 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/973603
PAGE BUFFER CIRCUIT AND MEMORY DEVICE INCLUDING THE SAME Dec 8, 2024 Pending
Array ( [id] => 20063072 [patent_doc_number] => 20250201294 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => RANDOMIZED REFRESH OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/970701 [patent_app_country] => US [patent_app_date] => 2024-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6108 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18970701 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/970701
RANDOMIZED REFRESH OPERATIONS Dec 4, 2024 Pending
Array ( [id] => 20588370 [patent_doc_number] => 20260073966 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => INTEGRATED CIRCUITS FOR LARGE-SCALE TRANSISTOR TENSOR OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/964417 [patent_app_country] => US [patent_app_date] => 2024-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 20168 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964417 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964417
INTEGRATED CIRCUITS FOR LARGE-SCALE TRANSISTOR TENSOR OPERATIONS Nov 29, 2024 Pending
Array ( [id] => 19850364 [patent_doc_number] => 20250095715 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD [patent_app_type] => utility [patent_app_number] => 18/964165 [patent_app_country] => US [patent_app_date] => 2024-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4107 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18964165 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/964165
NON-VOLATILE MEMORY DEVICE AND CONTROL METHOD Nov 28, 2024 Pending
Array ( [id] => 20476008 [patent_doc_number] => 20260018229 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-15 [patent_title] => CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/955528 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18955528 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/955528
CONTROLLER, MEMORY MODULE AND MEMORY SYSTEM Nov 20, 2024 Pending
Array ( [id] => 19803724 [patent_doc_number] => 20250069649 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => READ/WRITE CIRCUIT, READ/WRITE METHOD, AND MEMORY [patent_app_type] => utility [patent_app_number] => 18/948537 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13989 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948537 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948537
READ/WRITE CIRCUIT, READ/WRITE METHOD, AND MEMORY Nov 14, 2024 Pending
Array ( [id] => 20088578 [patent_doc_number] => 20250218514 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => NEUROMORPHIC MEMORY DEVICE AND NEUROMORPHIC SYSTEM USING THE SAME [patent_app_type] => utility [patent_app_number] => 18/939966 [patent_app_country] => US [patent_app_date] => 2024-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18939966 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/939966
NEUROMORPHIC MEMORY DEVICE AND NEUROMORPHIC SYSTEM USING THE SAME Nov 6, 2024 Pending
Array ( [id] => 19788273 [patent_doc_number] => 20250061952 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT OF MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/936422 [patent_app_country] => US [patent_app_date] => 2024-11-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3212 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18936422 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/936422
COMPLEMENTARY METAL OXIDE SEMICONDUCTOR CIRCUIT OF MEMORY DEVICE Nov 3, 2024 Pending
Array ( [id] => 20653945 [patent_doc_number] => 20260105969 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-16 [patent_title] => OFFSET CALIBRATION SCHEMES IN TIME-BASED 3D NAND-BASED VECTOR-MATRIX MULTIPLIER CIRCUIT [patent_app_type] => utility [patent_app_number] => 18/917095 [patent_app_country] => US [patent_app_date] => 2024-10-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 30584 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18917095 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/917095
OFFSET CALIBRATION SCHEMES IN TIME-BASED 3D NAND-BASED VECTOR-MATRIX MULTIPLIER CIRCUIT Oct 15, 2024 Pending
Array ( [id] => 19726894 [patent_doc_number] => 20250029645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => LOW RESISTANCE MTJ ANTIFUSE CIRCUITRY DESIGNS AND METHODS OF OPERATION [patent_app_type] => utility [patent_app_number] => 18/909363 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5682 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18909363 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/909363
LOW RESISTANCE MTJ ANTIFUSE CIRCUITRY DESIGNS AND METHODS OF OPERATION Oct 7, 2024 Pending
Array ( [id] => 20630346 [patent_doc_number] => 20260094634 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-04-02 [patent_title] => PREDECODERS WITH WRITE LOGIC BYPASS PATH AND MEMORY STRUCTURE INCLUDING PREDECODERS [patent_app_type] => utility [patent_app_number] => 18/901044 [patent_app_country] => US [patent_app_date] => 2024-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2144 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18901044 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/901044
PREDECODERS WITH WRITE LOGIC BYPASS PATH AND MEMORY STRUCTURE INCLUDING PREDECODERS Sep 29, 2024 Pending
Array ( [id] => 19712370 [patent_doc_number] => 20250022512 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-16 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/899645 [patent_app_country] => US [patent_app_date] => 2024-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 281 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18899645 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/899645
SEMICONDUCTOR MEMORY DEVICE Sep 26, 2024 Pending
Array ( [id] => 19698431 [patent_doc_number] => 20250016976 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/887835 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12316 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887835 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887835
SEMICONDUCTOR MEMORY DEVICE Sep 16, 2024 Pending
Array ( [id] => 20323036 [patent_doc_number] => 20250335124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-30 [patent_title] => MEMORY SYSTEMS, OPERATING METHODS FOR MEMORY SYSTEMS, CONTROLLER AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 18/826515 [patent_app_country] => US [patent_app_date] => 2024-09-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11356 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18826515 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/826515
MEMORY SYSTEMS, OPERATING METHODS FOR MEMORY SYSTEMS, CONTROLLER AND STORAGE MEDIUM Sep 5, 2024 Pending
Array ( [id] => 19664025 [patent_doc_number] => 20240431090 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-26 [patent_title] => Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices [patent_app_type] => utility [patent_app_number] => 18/821139 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5121 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18821139 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/821139
Integrated Memory Comprising Secondary Access Devices Between Digit Lines and Primary Access Devices Aug 29, 2024 Pending
Array ( [id] => 20019277 [patent_doc_number] => 20250157499 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-15 [patent_title] => REFERENCE VOLTAGE CALIBRATION APPARATUS IN MEMORY INTERFACE [patent_app_type] => utility [patent_app_number] => 18/820449 [patent_app_country] => US [patent_app_date] => 2024-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -10 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18820449 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/820449
REFERENCE VOLTAGE CALIBRATION APPARATUS IN MEMORY INTERFACE Aug 29, 2024 Pending
Array ( [id] => 20311770 [patent_doc_number] => 20250329399 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => MEMORY DEVICE AND CONTROL METHOD THEREOF [patent_app_type] => utility [patent_app_number] => 18/817167 [patent_app_country] => US [patent_app_date] => 2024-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18817167 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/817167
MEMORY DEVICE AND CONTROL METHOD THEREOF Aug 26, 2024 Pending
Array ( [id] => 19646258 [patent_doc_number] => 20240420778 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-12-19 [patent_title] => MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 18/815516 [patent_app_country] => US [patent_app_date] => 2024-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 39660 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 440 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18815516 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/815516
MEMORY SYSTEM Aug 25, 2024 Pending
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