Anthony Ho

Array ( [id] => 20522974 [patent_doc_number] => 20260047085 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-12 [patent_title] => MEMORY CELL INCLUDING DUAL-ANTIFUSE DEVICE, MEMORY STRUCTURE, AND OPERATING METHOD [patent_app_type] => utility [patent_app_number] => 18/800230 [patent_app_country] => US [patent_app_date] => 2024-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 75 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18800230 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20088585 [patent_doc_number] => 20250218521 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => NONVOLATILE MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/799934 [patent_app_country] => US [patent_app_date] => 2024-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14721 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 271 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18799934 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20514466 [patent_doc_number] => 20260038568 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-02-05 [patent_title] => MEMORY DEVICE HAVING WINDOW CENTERING [patent_app_type] => utility [patent_app_number] => 18/791225 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2417 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18791225 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19757806 [patent_doc_number] => 20250046371 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-06 [patent_title] => IN-MEMORY COMPUTATION DEVICE WITH AT LEAST AN IMPROVED DIGITAL DETECTOR FOR A MORE ACCURATE CURRENT MEASUREMENT [patent_app_type] => utility [patent_app_number] => 18/790867 [patent_app_country] => US [patent_app_date] => 2024-07-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19310 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 445 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18790867 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20746634 [patent_doc_number] => 12646553 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-06-02 [patent_title] => Read margin health evaluations for memory systems [patent_app_type] => utility [patent_app_number] => 18/787977 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 9004 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787977 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20501673 [patent_doc_number] => 20260031135 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-29 [patent_title] => COMBINATORY LOGIC FOR MULTI-LEVEL MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 18/787285 [patent_app_country] => US [patent_app_date] => 2024-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12135 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18787285 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19577346 [patent_doc_number] => 20240381638 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-14 [patent_title] => Memory Arrays Comprising Strings Of Memory Cells And Methods Used In Forming A Memory Array Comprising Strings Of Memory Cells [patent_app_type] => utility [patent_app_number] => 18/784152 [patent_app_country] => US [patent_app_date] => 2024-07-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6407 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18784152 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20488393 [patent_doc_number] => 20260024594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-22 [patent_title] => DYNAMIC READ DISTURB HANDLING USING SELECTIVE SCANNING [patent_app_type] => utility [patent_app_number] => 18/777850 [patent_app_country] => US [patent_app_date] => 2024-07-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4635 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18777850 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19559641 [patent_doc_number] => 20240371433 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-11-07 [patent_title] => MEMORY CIRCUITS, MEMORY STRUCTURES, AND METHODS FOR FABRICATING A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/772117 [patent_app_country] => US [patent_app_date] => 2024-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9320 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18772117 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20732954 [patent_doc_number] => 12640214 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-26 [patent_title] => Access line voltage ramp rate adjustment [patent_app_type] => utility [patent_app_number] => 18/771479 [patent_app_country] => US [patent_app_date] => 2024-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 0 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18771479 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19546126 [patent_doc_number] => 20240363162 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-31 [patent_title] => Methods for Reading Resistive States of Resistive Change Elements [patent_app_type] => utility [patent_app_number] => 18/770397 [patent_app_country] => US [patent_app_date] => 2024-07-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 75208 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -29 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18770397 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20002100 [patent_doc_number] => 20250140322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-01 [patent_title] => SELECTIVELY ERASING ONE OF MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING BY CREATING A PSEUDO PN JUNCTION [patent_app_type] => utility [patent_app_number] => 18/768974 [patent_app_country] => US [patent_app_date] => 2024-07-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9393 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18768974 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19531486 [patent_doc_number] => 20240355388 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-10-24 [patent_title] => MEMORY CELL INCLUDING PROGRAMMABLE RESISTORS WITH TRANSISTOR COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/758901 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758901 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20448105 [patent_doc_number] => 20260004829 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY CIRCUIT WITH BIT LINE CLAMPS [patent_app_type] => utility [patent_app_number] => 18/758730 [patent_app_country] => US [patent_app_date] => 2024-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3732 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18758730 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20448102 [patent_doc_number] => 20260004826 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-01-01 [patent_title] => MEMORY WITH REDUNDANT READ OPTIMIZATION [patent_app_type] => utility [patent_app_number] => 18/757302 [patent_app_country] => US [patent_app_date] => 2024-06-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 1259 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18757302 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20718114 [patent_doc_number] => 12633370 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-05-19 [patent_title] => Repairing defective columns of compute-in-memory and near-memory computing devices [patent_app_type] => utility [patent_app_number] => 18/755329 [patent_app_country] => US [patent_app_date] => 2024-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4276 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18755329 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19893046 [patent_doc_number] => 20250118358 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-10 [patent_title] => APPARATUSES AND METHODS FOR SINGLE AND MULTI MEMORY CELL ARCHITECTURES [patent_app_type] => utility [patent_app_number] => 18/746339 [patent_app_country] => US [patent_app_date] => 2024-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12919 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18746339 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19820704 [patent_doc_number] => 20250078911 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 18/745943 [patent_app_country] => US [patent_app_date] => 2024-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 19219 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18745943 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20581210 [patent_doc_number] => 12573464 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-03-10 [patent_title] => Memory controller useable for a dynamic random access memory (DRAM) health monitor [patent_app_type] => utility [patent_app_number] => 18/736883 [patent_app_country] => US [patent_app_date] => 2024-06-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 3875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18736883 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19467696 [patent_doc_number] => 20240321366 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-09-26 [patent_title] => NONVOLATILE MEMORY DEVICE, STORAGE DEVICE INCLUDING NONVOLATILE MEMORY DEVICE, AND OPERATING METHOD OF STORAGE DEVICE [patent_app_type] => utility [patent_app_number] => 18/734833 [patent_app_country] => US [patent_app_date] => 2024-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 18042 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -11 [patent_words_short_claim] => 74 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18734833 [rel_patent_id] =>[rel_patent_doc_number] =>)