Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 13767531 [patent_doc_number] => 10176109 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-08 [patent_title] => Permuted memory access mapping [patent_app_type] => utility [patent_app_number] => 15/493035 [patent_app_country] => US [patent_app_date] => 2017-04-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8346 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15493035 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/493035
Permuted memory access mapping Apr 19, 2017 Issued
Array ( [id] => 12845338 [patent_doc_number] => 20180173619 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-06-21 [patent_title] => System and Method for Distributed Logical to Physical Address Mapping [patent_app_type] => utility [patent_app_number] => 15/491917 [patent_app_country] => US [patent_app_date] => 2017-04-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9234 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 262 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15491917 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/491917
System and Method for Distributed Logical to Physical Address Mapping Apr 18, 2017 Abandoned
Array ( [id] => 15952533 [patent_doc_number] => 10664171 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Memory systems and methods including training, data organizing, and/or shadowing [patent_app_type] => utility [patent_app_number] => 15/483804 [patent_app_country] => US [patent_app_date] => 2017-04-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 7550 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15483804 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/483804
Memory systems and methods including training, data organizing, and/or shadowing Apr 9, 2017 Issued
Array ( [id] => 17757395 [patent_doc_number] => 11397687 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-07-26 [patent_title] => Flash-integrated high bandwidth memory appliance [patent_app_type] => utility [patent_app_number] => 15/481147 [patent_app_country] => US [patent_app_date] => 2017-04-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5011 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 265 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15481147 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/481147
Flash-integrated high bandwidth memory appliance Apr 5, 2017 Issued
Array ( [id] => 11731234 [patent_doc_number] => 20170192677 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'ACCELERATED NON-VOLATILE MEMORY RECIRCULATION PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/466568 [patent_app_country] => US [patent_app_date] => 2017-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 13388 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15466568 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/466568
Accelerated non-volatile memory recirculation processing Mar 21, 2017 Issued
Array ( [id] => 13432399 [patent_doc_number] => 20180267742 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-09-20 [patent_title] => TECHNOLOGIES FOR FINE-GRAINED COMPLETION TRACKING OF MEMORY BUFFER ACCESSES [patent_app_type] => utility [patent_app_number] => 15/463005 [patent_app_country] => US [patent_app_date] => 2017-03-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9026 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -26 [patent_words_short_claim] => 123 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15463005 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/463005
Technologies for fine-grained completion tracking of memory buffer accesses Mar 19, 2017 Issued
Array ( [id] => 13055149 [patent_doc_number] => 10048965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-08-14 [patent_title] => Instruction and logic for a binary translation mechanism for control-flow security [patent_app_type] => utility [patent_app_number] => 15/455886 [patent_app_country] => US [patent_app_date] => 2017-03-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 14661 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15455886 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/455886
Instruction and logic for a binary translation mechanism for control-flow security Mar 9, 2017 Issued
Array ( [id] => 15214621 [patent_doc_number] => 20190369997 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => SIMULATION DEVICE, SIMULATION METHOD, AND COMPUTER READABLE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/475308 [patent_app_country] => US [patent_app_date] => 2017-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -5 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16475308 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/475308
SIMULATION DEVICE, SIMULATION METHOD, AND COMPUTER READABLE MEDIUM Feb 27, 2017 Abandoned
Array ( [id] => 12290865 [patent_doc_number] => 09933962 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2018-04-03 [patent_title] => Method for achieving sequential I/O performance from a random workload [patent_app_type] => utility [patent_app_number] => 15/443763 [patent_app_country] => US [patent_app_date] => 2017-02-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 4622 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15443763 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/443763
Method for achieving sequential I/O performance from a random workload Feb 26, 2017 Issued
Array ( [id] => 12229005 [patent_doc_number] => 09916250 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-13 [patent_title] => 'Method for using service level objectives to dynamically allocate cache resources among competing workloads' [patent_app_type] => utility [patent_app_number] => 15/437635 [patent_app_country] => US [patent_app_date] => 2017-02-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7622 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 172 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15437635 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/437635
Method for using service level objectives to dynamically allocate cache resources among competing workloads Feb 20, 2017 Issued
Array ( [id] => 11665266 [patent_doc_number] => 20170153985 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-06-01 [patent_title] => 'METHOD TO EFFICIENTLY IMPLEMENT SYNCHRONIZATION USING SOFTWARE MANAGED ADDRESS TRANSLATION' [patent_app_type] => utility [patent_app_number] => 15/432307 [patent_app_country] => US [patent_app_date] => 2017-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5015 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15432307 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/432307
Method to efficiently implement synchronization using software managed address translation Feb 13, 2017 Issued
Array ( [id] => 14249939 [patent_doc_number] => 10275169 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Shared memory in memory isolated partitions [patent_app_type] => utility [patent_app_number] => 15/409267 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8871 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409267 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409267
Shared memory in memory isolated partitions Jan 17, 2017 Issued
Array ( [id] => 13817453 [patent_doc_number] => 10185495 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-01-22 [patent_title] => Block storage device having hierarchical disks with different access frequencies [patent_app_type] => utility [patent_app_number] => 15/409052 [patent_app_country] => US [patent_app_date] => 2017-01-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 26 [patent_no_of_words] => 13419 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 341 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15409052 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/409052
Block storage device having hierarchical disks with different access frequencies Jan 17, 2017 Issued
Array ( [id] => 11591523 [patent_doc_number] => 20170115934 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'LOGICAL BLOCK ADDRESSES USED FOR EXECUTING HOST COMMANDS' [patent_app_type] => utility [patent_app_number] => 15/401570 [patent_app_country] => US [patent_app_date] => 2017-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5572 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15401570 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/401570
Logical block addresses used for executing host commands Jan 8, 2017 Issued
Array ( [id] => 12249188 [patent_doc_number] => 09921964 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Demote instruction for relinquishing cache line ownership' [patent_app_type] => utility [patent_app_number] => 15/400971 [patent_app_country] => US [patent_app_date] => 2017-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2928 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400971 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400971
Demote instruction for relinquishing cache line ownership Jan 6, 2017 Issued
Array ( [id] => 12249189 [patent_doc_number] => 09921965 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-03-20 [patent_title] => 'Demote instruction for relinquishing cache line ownership' [patent_app_type] => utility [patent_app_number] => 15/400973 [patent_app_country] => US [patent_app_date] => 2017-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 2928 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15400973 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/400973
Demote instruction for relinquishing cache line ownership Jan 6, 2017 Issued
Array ( [id] => 11591474 [patent_doc_number] => 20170115885 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-27 [patent_title] => 'Self-addressing Memory' [patent_app_type] => utility [patent_app_number] => 15/397107 [patent_app_country] => US [patent_app_date] => 2017-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 14332 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15397107 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/397107
Self-addressing memory Jan 2, 2017 Issued
Array ( [id] => 16185924 [patent_doc_number] => 10719256 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-07-21 [patent_title] => Performance of deduplication storage systems [patent_app_type] => utility [patent_app_number] => 15/395137 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 20 [patent_no_of_words] => 7852 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 419 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395137 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395137
Performance of deduplication storage systems Dec 29, 2016 Issued
Array ( [id] => 11731247 [patent_doc_number] => 20170192690 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-07-06 [patent_title] => 'METHOD, ELECTRONIC DEVICE AND COMPUTER PROGRAM PRODUCT FOR DATA PROCESSING' [patent_app_type] => utility [patent_app_number] => 15/395228 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 8306 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395228 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395228
Method, electronic device and computer program product for data processing Dec 29, 2016 Issued
Array ( [id] => 12891394 [patent_doc_number] => 20180188973 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-07-05 [patent_title] => PROCESSOR IN NON-VOLATILE STORAGE MEMORY [patent_app_type] => utility [patent_app_number] => 15/395474 [patent_app_country] => US [patent_app_date] => 2016-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10409 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15395474 [rel_patent_id] =>[rel_patent_doc_number] =>)
15/395474
Processor in non-volatile storage memory Dec 29, 2016 Issued
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