Anthony J Green
Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )
Most Active Art Unit | 1731 |
Art Unit(s) | 1754, 2899, 1108, 1793, 1731, 1755 |
Total Applications | 4596 |
Issued Applications | 3675 |
Pending Applications | 315 |
Abandoned Applications | 605 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 234819
[patent_doc_number] => 07600084
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[patent_issue_date] => 2009-10-06
[patent_title] => 'Register file with integrated routing to execution units for multi-threaded processors'
[patent_app_type] => utility
[patent_app_number] => 11/956144
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[pdf_file] => patents/07/600/07600084.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/956144 | Register file with integrated routing to execution units for multi-threaded processors | Dec 12, 2007 | Issued |
Array
(
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[patent_doc_number] => 20090150593
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[patent_kind] => A1
[patent_issue_date] => 2009-06-11
[patent_title] => 'DYNAMTIC STORAGE HIERARACHY MANAGEMENT'
[patent_app_type] => utility
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/954145 | Dynamtic storage hierarachy management | Dec 10, 2007 | Issued |
Array
(
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[patent_issue_date] => 2008-04-17
[patent_title] => 'Integrated circuit memory device having delayed write timing based on read response time'
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[patent_app_number] => 11/953803
[patent_app_country] => US
[patent_app_date] => 2007-12-10
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[firstpage_image] =>[orig_patent_app_number] => 11953803
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/953803 | Integrated circuit memory device having delayed write timing based on read response time | Dec 9, 2007 | Issued |
Array
(
[id] => 5577129
[patent_doc_number] => 20090144491
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[patent_kind] => A1
[patent_issue_date] => 2009-06-04
[patent_title] => 'METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASED CACHE'
[patent_app_type] => utility
[patent_app_number] => 11/949859
[patent_app_country] => US
[patent_app_date] => 2007-12-04
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[firstpage_image] =>[orig_patent_app_number] => 11949859
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/949859 | Method and system for implementing prioritized refresh of DRAM based cache | Dec 3, 2007 | Issued |
Array
(
[id] => 4443307
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[patent_issue_date] => 2011-03-01
[patent_title] => 'Embedded system and page relocation method therefor'
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Array
(
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[patent_title] => 'Protected cache architecture and secure programming paradigm to protect applications'
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[firstpage_image] =>[orig_patent_app_number] => 11998902
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/998902 | Protected cache architecture and secure programming paradigm to protect applications | Dec 2, 2007 | Issued |
Array
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[patent_title] => 'Direct interconnection between processor and memory component'
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Array
(
[id] => 7520997
[patent_doc_number] => 07975105
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[patent_issue_date] => 2011-07-05
[patent_title] => 'Solid state storage devices with changeable capacity'
[patent_app_type] => utility
[patent_app_number] => 11/949748
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/949748 | Solid state storage devices with changeable capacity | Dec 2, 2007 | Issued |
Array
(
[id] => 5577157
[patent_doc_number] => 20090144519
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[patent_issue_date] => 2009-06-04
[patent_title] => 'Multithreaded Processor with Lock Indicator'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/949284 | Multithreaded processor with lock indicator | Dec 2, 2007 | Issued |
Array
(
[id] => 8273097
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[patent_title] => 'Memory allocation in a mobile device'
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[patent_app_number] => 11/945241
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[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11945241
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/945241 | Memory allocation in a mobile device | Nov 25, 2007 | Issued |
Array
(
[id] => 8546348
[patent_doc_number] => 08321650
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[patent_issue_date] => 2012-11-27
[patent_title] => 'Alignment-unit-based virtual formatting methods and devices employing the methods'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/986959 | Alignment-unit-based virtual formatting methods and devices employing the methods | Nov 25, 2007 | Issued |
Array
(
[id] => 175564
[patent_doc_number] => 07660947
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[patent_title] => 'Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner'
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Array
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[id] => 355480
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[patent_title] => 'System, method and storage medium for prefetching via memory block tags'
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Array
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Array
(
[id] => 4706317
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/925212 | SYSTEMS AND METHODS FOR MANAGING LOCAL AND REMOTE MEMORY ACCESS | Oct 25, 2007 | Abandoned |
Array
(
[id] => 4653292
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[patent_title] => 'Direct Deposit Using Locking Cache'
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864091 | STAGING METHOD FOR DISK ARRAY APPARATUS | Sep 27, 2007 | Abandoned |