Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 234819 [patent_doc_number] => 07600084 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2009-10-06 [patent_title] => 'Register file with integrated routing to execution units for multi-threaded processors' [patent_app_type] => utility [patent_app_number] => 11/956144 [patent_app_country] => US [patent_app_date] => 2007-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 2554 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/600/07600084.pdf [firstpage_image] =>[orig_patent_app_number] => 11956144 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/956144
Register file with integrated routing to execution units for multi-threaded processors Dec 12, 2007 Issued
Array ( [id] => 5424137 [patent_doc_number] => 20090150593 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-11 [patent_title] => 'DYNAMTIC STORAGE HIERARACHY MANAGEMENT' [patent_app_type] => utility [patent_app_number] => 11/954145 [patent_app_country] => US [patent_app_date] => 2007-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 10233 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0150/20090150593.pdf [firstpage_image] =>[orig_patent_app_number] => 11954145 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/954145
Dynamtic storage hierarachy management Dec 10, 2007 Issued
Array ( [id] => 4747305 [patent_doc_number] => 20080091907 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-04-17 [patent_title] => 'Integrated circuit memory device having delayed write timing based on read response time' [patent_app_type] => utility [patent_app_number] => 11/953803 [patent_app_country] => US [patent_app_date] => 2007-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 45 [patent_figures_cnt] => 45 [patent_no_of_words] => 9534 [patent_no_of_claims] => 50 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0091/20080091907.pdf [firstpage_image] =>[orig_patent_app_number] => 11953803 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/953803
Integrated circuit memory device having delayed write timing based on read response time Dec 9, 2007 Issued
Array ( [id] => 5577129 [patent_doc_number] => 20090144491 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'METHOD AND SYSTEM FOR IMPLEMENTING PRIORITIZED REFRESH OF DRAM BASED CACHE' [patent_app_type] => utility [patent_app_number] => 11/949859 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3481 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144491.pdf [firstpage_image] =>[orig_patent_app_number] => 11949859 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949859
Method and system for implementing prioritized refresh of DRAM based cache Dec 3, 2007 Issued
Array ( [id] => 4443307 [patent_doc_number] => 07900018 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-01 [patent_title] => 'Embedded system and page relocation method therefor' [patent_app_type] => utility [patent_app_number] => 11/949879 [patent_app_country] => US [patent_app_date] => 2007-12-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3246 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/900/07900018.pdf [firstpage_image] =>[orig_patent_app_number] => 11949879 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949879
Embedded system and page relocation method therefor Dec 3, 2007 Issued
Array ( [id] => 4836513 [patent_doc_number] => 20080133842 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-05 [patent_title] => 'Protected cache architecture and secure programming paradigm to protect applications' [patent_app_type] => utility [patent_app_number] => 11/998902 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5047 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0133/20080133842.pdf [firstpage_image] =>[orig_patent_app_number] => 11998902 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/998902
Protected cache architecture and secure programming paradigm to protect applications Dec 2, 2007 Issued
Array ( [id] => 8285620 [patent_doc_number] => 08219738 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-07-10 [patent_title] => 'Direct interconnection between processor and memory component' [patent_app_type] => utility [patent_app_number] => 11/949521 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10299 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11949521 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949521
Direct interconnection between processor and memory component Dec 2, 2007 Issued
Array ( [id] => 7520997 [patent_doc_number] => 07975105 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-05 [patent_title] => 'Solid state storage devices with changeable capacity' [patent_app_type] => utility [patent_app_number] => 11/949748 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3830 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/975/07975105.pdf [firstpage_image] =>[orig_patent_app_number] => 11949748 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949748
Solid state storage devices with changeable capacity Dec 2, 2007 Issued
Array ( [id] => 5577157 [patent_doc_number] => 20090144519 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-06-04 [patent_title] => 'Multithreaded Processor with Lock Indicator' [patent_app_type] => utility [patent_app_number] => 11/949284 [patent_app_country] => US [patent_app_date] => 2007-12-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5974 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0144/20090144519.pdf [firstpage_image] =>[orig_patent_app_number] => 11949284 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/949284
Multithreaded processor with lock indicator Dec 2, 2007 Issued
Array ( [id] => 8273097 [patent_doc_number] => 08214619 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-07-03 [patent_title] => 'Memory allocation in a mobile device' [patent_app_type] => utility [patent_app_number] => 11/945241 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 9608 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 202 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11945241 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/945241
Memory allocation in a mobile device Nov 25, 2007 Issued
Array ( [id] => 8546348 [patent_doc_number] => 08321650 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-11-27 [patent_title] => 'Alignment-unit-based virtual formatting methods and devices employing the methods' [patent_app_type] => utility [patent_app_number] => 11/986959 [patent_app_country] => US [patent_app_date] => 2007-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 106 [patent_figures_cnt] => 111 [patent_no_of_words] => 41547 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11986959 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986959
Alignment-unit-based virtual formatting methods and devices employing the methods Nov 25, 2007 Issued
Array ( [id] => 175564 [patent_doc_number] => 07660947 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-02-09 [patent_title] => 'Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner' [patent_app_type] => utility [patent_app_number] => 11/986226 [patent_app_country] => US [patent_app_date] => 2007-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 17455 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/660/07660947.pdf [firstpage_image] =>[orig_patent_app_number] => 11986226 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/986226
Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner Nov 19, 2007 Issued
Array ( [id] => 355480 [patent_doc_number] => 07493453 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-02-17 [patent_title] => 'System, method and storage medium for prefetching via memory block tags' [patent_app_type] => utility [patent_app_number] => 11/936414 [patent_app_country] => US [patent_app_date] => 2007-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5443 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/493/07493453.pdf [firstpage_image] =>[orig_patent_app_number] => 11936414 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/936414
System, method and storage medium for prefetching via memory block tags Nov 6, 2007 Issued
Array ( [id] => 4454885 [patent_doc_number] => 07966443 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-06-21 [patent_title] => 'Memory systems including memory devices coupled together in a daisy-chained arrangement' [patent_app_type] => utility [patent_app_number] => 11/933445 [patent_app_country] => US [patent_app_date] => 2007-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 31 [patent_figures_cnt] => 38 [patent_no_of_words] => 22459 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/966/07966443.pdf [firstpage_image] =>[orig_patent_app_number] => 11933445 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/933445
Memory systems including memory devices coupled together in a daisy-chained arrangement Oct 31, 2007 Issued
Array ( [id] => 4706317 [patent_doc_number] => 20080065841 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-03-13 [patent_title] => 'Method and apparatus for executing dynamic memory management with object-oriented program' [patent_app_type] => utility [patent_app_number] => 11/980447 [patent_app_country] => US [patent_app_date] => 2007-10-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2812 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0065/20080065841.pdf [firstpage_image] =>[orig_patent_app_number] => 11980447 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/980447
Method and apparatus for executing dynamic memory management with object-oriented program Oct 30, 2007 Issued
Array ( [id] => 5332666 [patent_doc_number] => 20090113143 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2009-04-30 [patent_title] => 'SYSTEMS AND METHODS FOR MANAGING LOCAL AND REMOTE MEMORY ACCESS' [patent_app_type] => utility [patent_app_number] => 11/925212 [patent_app_country] => US [patent_app_date] => 2007-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4659 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0113/20090113143.pdf [firstpage_image] =>[orig_patent_app_number] => 11925212 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/925212
SYSTEMS AND METHODS FOR MANAGING LOCAL AND REMOTE MEMORY ACCESS Oct 25, 2007 Abandoned
Array ( [id] => 4653292 [patent_doc_number] => 20080040549 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-02-14 [patent_title] => 'Direct Deposit Using Locking Cache' [patent_app_type] => utility [patent_app_number] => 11/875407 [patent_app_country] => US [patent_app_date] => 2007-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 2580 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0040/20080040549.pdf [firstpage_image] =>[orig_patent_app_number] => 11875407 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/875407
Direct deposit using locking cache Oct 18, 2007 Issued
Array ( [id] => 237676 [patent_doc_number] => 07596665 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2009-09-29 [patent_title] => 'Mechanism for a processor to use locking cache as part of system memory' [patent_app_type] => utility [patent_app_number] => 11/874513 [patent_app_country] => US [patent_app_date] => 2007-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2263 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/596/07596665.pdf [firstpage_image] =>[orig_patent_app_number] => 11874513 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/874513
Mechanism for a processor to use locking cache as part of system memory Oct 17, 2007 Issued
Array ( [id] => 599902 [patent_doc_number] => 07441080 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2008-10-21 [patent_title] => 'Method of and system for controlling attributes of a plurality of storage devices' [patent_app_type] => utility [patent_app_number] => 11/974383 [patent_app_country] => US [patent_app_date] => 2007-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 26 [patent_no_of_words] => 5267 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 92 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/441/07441080.pdf [firstpage_image] =>[orig_patent_app_number] => 11974383 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/974383
Method of and system for controlling attributes of a plurality of storage devices Oct 11, 2007 Issued
Array ( [id] => 4881810 [patent_doc_number] => 20080155193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2008-06-26 [patent_title] => 'STAGING METHOD FOR DISK ARRAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 11/864091 [patent_app_country] => US [patent_app_date] => 2007-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3989 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0155/20080155193.pdf [firstpage_image] =>[orig_patent_app_number] => 11864091 [rel_patent_id] =>[rel_patent_doc_number] =>)
11/864091
STAGING METHOD FOR DISK ARRAY APPARATUS Sep 27, 2007 Abandoned
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