Anthony J Green
Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )
Most Active Art Unit | 1731 |
Art Unit(s) | 1754, 2899, 1108, 1793, 1731, 1755 |
Total Applications | 4596 |
Issued Applications | 3675 |
Pending Applications | 315 |
Abandoned Applications | 605 |
Applications
Application number | Title of the application | Filing Date | Status |
---|---|---|---|
Array
(
[id] => 18861
[patent_doc_number] => 07809916
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2010-10-05
[patent_title] => 'Method for dynamically refining locks in resizable concurrent hashing'
[patent_app_type] => utility
[patent_app_number] => 11/863901
[patent_app_country] => US
[patent_app_date] => 2007-09-28
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[patent_current_assignee] =>[type] => patent
[pdf_file] => patents/07/809/07809916.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863901
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863901 | Method for dynamically refining locks in resizable concurrent hashing | Sep 27, 2007 | Issued |
Array
(
[id] => 4589493
[patent_doc_number] => 07861053
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[patent_kind] => B2
[patent_issue_date] => 2010-12-28
[patent_title] => 'Supporting un-buffered memory modules on a platform configured for registered memory modules'
[patent_app_type] => utility
[patent_app_number] => 11/863838
[patent_app_country] => US
[patent_app_date] => 2007-09-28
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[pdf_file] => patents/07/861/07861053.pdf
[firstpage_image] =>[orig_patent_app_number] => 11863838
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863838 | Supporting un-buffered memory modules on a platform configured for registered memory modules | Sep 27, 2007 | Issued |
Array
(
[id] => 4527545
[patent_doc_number] => 07934072
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2011-04-26
[patent_title] => 'Solid state storage reclamation apparatus and method'
[patent_app_type] => utility
[patent_app_number] => 11/864106
[patent_app_country] => US
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[pdf_file] => patents/07/934/07934072.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864106
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864106 | Solid state storage reclamation apparatus and method | Sep 27, 2007 | Issued |
Array
(
[id] => 5430200
[patent_doc_number] => 20090089510
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR'
[patent_app_type] => utility
[patent_app_number] => 11/864363
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
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[pdf_file] => publications/A1/0089/20090089510.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864363
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864363 | SPECULATIVE READ IN A CACHE COHERENT MICROPROCESSOR | Sep 27, 2007 | Abandoned |
Array
(
[id] => 8558127
[patent_doc_number] => 08332613
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2012-12-11
[patent_title] => 'Methods and systems for managing I/O requests to minimize disruption required for data encapsulation and de-encapsulation'
[patent_app_type] => utility
[patent_app_number] => 11/863745
[patent_app_country] => US
[patent_app_date] => 2007-09-28
[patent_effective_date] => 0000-00-00
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[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 11863745
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/863745 | Methods and systems for managing I/O requests to minimize disruption required for data encapsulation and de-encapsulation | Sep 27, 2007 | Issued |
Array
(
[id] => 5430185
[patent_doc_number] => 20090089495
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2009-04-02
[patent_title] => 'NON-BLOCKING VARIABLE SIZE RECYCLABLE BUFFER MANAGEMENT'
[patent_app_type] => utility
[patent_app_number] => 11/864211
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[patent_app_date] => 2007-09-28
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[pdf_file] => publications/A1/0089/20090089495.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864211
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864211 | Non-blocking variable size recyclable buffer management | Sep 27, 2007 | Issued |
Array
(
[id] => 7972021
[patent_doc_number] => 07941588
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[patent_issue_date] => 2011-05-10
[patent_title] => 'Multi-level nonvolatile semiconductor memory device'
[patent_app_type] => utility
[patent_app_number] => 11/864074
[patent_app_country] => US
[patent_app_date] => 2007-09-28
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[pdf_file] => patents/07/941/07941588.pdf
[firstpage_image] =>[orig_patent_app_number] => 11864074
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/864074 | Multi-level nonvolatile semiconductor memory device | Sep 27, 2007 | Issued |
Array
(
[id] => 8758
[patent_doc_number] => 07818532
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2010-10-19
[patent_title] => 'Method and system for creating and restoring an image file'
[patent_app_type] => utility
[patent_app_number] => 11/862910
[patent_app_country] => US
[patent_app_date] => 2007-09-27
[patent_effective_date] => 0000-00-00
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[pdf_file] => patents/07/818/07818532.pdf
[firstpage_image] =>[orig_patent_app_number] => 11862910
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/862910 | Method and system for creating and restoring an image file | Sep 26, 2007 | Issued |
Array
(
[id] => 5454508
[patent_doc_number] => 20090070545
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[patent_issue_date] => 2009-03-12
[patent_title] => 'PROCESSING SYSTEM IMPLEMENTING VARIABLE PAGE SIZE MEMORY ORGANIZATION USING A MULTIPLE PAGE PER ENTRY TRANSLATION LOOKASIDE BUFFER'
[patent_app_type] => utility
[patent_app_number] => 11/853451
[patent_app_country] => US
[patent_app_date] => 2007-09-11
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[firstpage_image] =>[orig_patent_app_number] => 11853451
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/853451 | Processing system implementing variable page size memory organization using a multiple page per entry translation lookaside buffer | Sep 10, 2007 | Issued |
Array
(
[id] => 5200720
[patent_doc_number] => 20070300038
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[patent_issue_date] => 2007-12-27
[patent_title] => 'Memory Controller for Non-Homogeneous Memory System'
[patent_app_type] => utility
[patent_app_number] => 11/852996
[patent_app_country] => US
[patent_app_date] => 2007-09-10
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[firstpage_image] =>[orig_patent_app_number] => 11852996
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/852996 | Memory controller for non-homogeneous memory system | Sep 9, 2007 | Issued |
Array
(
[id] => 4671559
[patent_doc_number] => 20080046620
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[patent_title] => 'Handling of the Transmit Enable Signal in a Dynamic Random Access Memory Controller'
[patent_app_type] => utility
[patent_app_number] => 11/849548
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[firstpage_image] =>[orig_patent_app_number] => 11849548
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/849548 | Handling of the transmit enable signal in a dynamic random access memory controller | Sep 3, 2007 | Issued |
Array
(
[id] => 5232392
[patent_doc_number] => 20070294501
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[patent_issue_date] => 2007-12-20
[patent_title] => 'Cooperative memory management'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/894434 | Cooperative memory management allowing program request and release memory as needed | Aug 19, 2007 | Issued |
Array
(
[id] => 146495
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[patent_title] => 'System and method for sharing memory by heterogeneous processors'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/840284 | System and method for sharing memory by heterogeneous processors | Aug 16, 2007 | Issued |
Array
(
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[patent_title] => 'Memory controller, nonvolatile memory device, access device, and nonvolatile memory system'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 12/376153 | Memory controller, nonvolatile memory device, access device, and nonvolatile memory system | Jul 31, 2007 | Issued |
Array
(
[id] => 4940617
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[patent_title] => 'MULTIPATH ACCESSIBLE SEMICONDUCTOR MEMORY DEVICE WITH HOST INTERFACE BETWEEN PROCESSORS'
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[firstpage_image] =>[orig_patent_app_number] => 11829859
[rel_patent_id] =>[rel_patent_doc_number] =>) 11/829859 | Multipath accessible semiconductor memory device with host interface between processors | Jul 26, 2007 | Issued |
Array
(
[id] => 18808
[patent_doc_number] => 07809889
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[patent_title] => 'High performance multilevel cache hierarchy'
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/779784 | High performance multilevel cache hierarchy | Jul 17, 2007 | Issued |
Array
(
[id] => 5292094
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/779853 | Processing system having a supported page size information register | Jul 17, 2007 | Issued |
Array
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Array
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 11/777310 | Digital electronic device capable of memory formatting, a method of memory formatting, digital electronic device having a function of storing and method for storing thereof | Jul 12, 2007 | Issued |