Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 6900394 [patent_doc_number] => 20010010070 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-26 [patent_title] => 'System and method for dynamically resynchronizing backup data' [patent_app_type] => new [patent_app_number] => 09/785926 [patent_app_country] => US [patent_app_date] => 2001-02-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5158 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 298 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0010/20010010070.pdf [firstpage_image] =>[orig_patent_app_number] => 09785926 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/785926
System and method for dynamically resynchronizing backup data Feb 14, 2001 Issued
Array ( [id] => 5791386 [patent_doc_number] => 20020161932 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-10-31 [patent_title] => 'System and method for managing memory compression transparent to an operating system' [patent_app_type] => new [patent_app_number] => 09/782495 [patent_app_country] => US [patent_app_date] => 2001-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5712 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 129 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0161/20020161932.pdf [firstpage_image] =>[orig_patent_app_number] => 09782495 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/782495
System and method for managing memory compression transparent to an operating system Feb 12, 2001 Issued
Array ( [id] => 1138919 [patent_doc_number] => 06789158 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2004-09-07 [patent_title] => 'Method of rewriting program in a flash microcomputer' [patent_app_type] => B2 [patent_app_number] => 09/770459 [patent_app_country] => US [patent_app_date] => 2001-01-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 5585 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/789/06789158.pdf [firstpage_image] =>[orig_patent_app_number] => 09770459 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/770459
Method of rewriting program in a flash microcomputer Jan 28, 2001 Issued
Array ( [id] => 6085536 [patent_doc_number] => 20020083281 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-27 [patent_title] => 'Write logging in mirrored disk subsystems' [patent_app_type] => new [patent_app_number] => 09/746806 [patent_app_country] => US [patent_app_date] => 2000-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4742 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0083/20020083281.pdf [firstpage_image] =>[orig_patent_app_number] => 09746806 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/746806
Write logging in mirrored disk subsystems Dec 21, 2000 Issued
Array ( [id] => 1438663 [patent_doc_number] => 06356977 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2002-03-12 [patent_title] => 'System and method for on-line, real time, data migration' [patent_app_type] => B2 [patent_app_number] => 09/735023 [patent_app_country] => US [patent_app_date] => 2000-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 11693 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356977.pdf [firstpage_image] =>[orig_patent_app_number] => 09735023 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735023
System and method for on-line, real time, data migration Dec 11, 2000 Issued
Array ( [id] => 6211756 [patent_doc_number] => 20020073405 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-06-13 [patent_title] => 'System and method for the discovery and use of repetitively accessed data' [patent_app_type] => new [patent_app_number] => 09/735027 [patent_app_country] => US [patent_app_date] => 2000-12-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8040 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0073/20020073405.pdf [firstpage_image] =>[orig_patent_app_number] => 09735027 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/735027
System and method for the discovery and use of repetitively accessed data Dec 10, 2000 Issued
Array ( [id] => 6875756 [patent_doc_number] => 20010000083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-03-29 [patent_title] => 'Shared cache parsing and pre-fetch' [patent_app_type] => new-utility [patent_app_number] => 09/726679 [patent_app_country] => US [patent_app_date] => 2000-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2945 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0000/20010000083.pdf [firstpage_image] =>[orig_patent_app_number] => 09726679 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/726679
Shared cache parsing and pre-fetch Nov 28, 2000 Issued
Array ( [id] => 1584753 [patent_doc_number] => 06449688 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-10 [patent_title] => 'Computer system and process for transferring streams of data between multiple storage units and multiple applications in a scalable and reliable manner' [patent_app_type] => B1 [patent_app_number] => 09/724327 [patent_app_country] => US [patent_app_date] => 2000-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 20265 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 318 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/449/06449688.pdf [firstpage_image] =>[orig_patent_app_number] => 09724327 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/724327
Computer system and process for transferring streams of data between multiple storage units and multiple applications in a scalable and reliable manner Nov 27, 2000 Issued
Array ( [id] => 1430387 [patent_doc_number] => 06526489 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-02-25 [patent_title] => 'Data storage apparatus with improved security process and partition allocation funds' [patent_app_type] => B1 [patent_app_number] => 09/711077 [patent_app_country] => US [patent_app_date] => 2000-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4489 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 327 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/526/06526489.pdf [firstpage_image] =>[orig_patent_app_number] => 09711077 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/711077
Data storage apparatus with improved security process and partition allocation funds Nov 13, 2000 Issued
Array ( [id] => 1214417 [patent_doc_number] => 06715053 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-30 [patent_title] => 'Method and apparatus for controlling memory client access to address ranges in a memory pool' [patent_app_type] => B1 [patent_app_number] => 09/699858 [patent_app_country] => US [patent_app_date] => 2000-10-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2774 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 219 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/715/06715053.pdf [firstpage_image] =>[orig_patent_app_number] => 09699858 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/699858
Method and apparatus for controlling memory client access to address ranges in a memory pool Oct 29, 2000 Issued
09/699811 Storage controller with the disk drive and the RAM in a hybrid architecture Oct 29, 2000 Abandoned
Array ( [id] => 1183551 [patent_doc_number] => 06751711 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Methods and systems for process rollback in a shared memory parallel processor computing environment' [patent_app_type] => B1 [patent_app_number] => 09/696957 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6576 [patent_no_of_claims] => 37 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 93 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751711.pdf [firstpage_image] =>[orig_patent_app_number] => 09696957 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696957
Methods and systems for process rollback in a shared memory parallel processor computing environment Oct 26, 2000 Issued
Array ( [id] => 1024886 [patent_doc_number] => 06889306 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-05-03 [patent_title] => 'Microprocessor and program modification method in the microprocessor' [patent_app_type] => utility [patent_app_number] => 09/697429 [patent_app_country] => US [patent_app_date] => 2000-10-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 4515 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/889/06889306.pdf [firstpage_image] =>[orig_patent_app_number] => 09697429 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697429
Microprocessor and program modification method in the microprocessor Oct 26, 2000 Issued
Array ( [id] => 1225574 [patent_doc_number] => 06704843 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-09 [patent_title] => 'Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange' [patent_app_type] => B1 [patent_app_number] => 09/696890 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 6439 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/704/06704843.pdf [firstpage_image] =>[orig_patent_app_number] => 09696890 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696890
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange Oct 25, 2000 Issued
Array ( [id] => 1308819 [patent_doc_number] => 06629210 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Intelligent cache management mechanism via processor access sequence analysis' [patent_app_type] => B1 [patent_app_number] => 09/696888 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4839 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629210.pdf [firstpage_image] =>[orig_patent_app_number] => 09696888 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696888
Intelligent cache management mechanism via processor access sequence analysis Oct 25, 2000 Issued
Array ( [id] => 1339234 [patent_doc_number] => 06601144 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis' [patent_app_type] => B1 [patent_app_number] => 09/696912 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4954 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 118 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601144.pdf [firstpage_image] =>[orig_patent_app_number] => 09696912 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696912
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis Oct 25, 2000 Issued
Array ( [id] => 1179102 [patent_doc_number] => 06757801 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-29 [patent_title] => 'Method to modify that an operation needs to be done on a file system' [patent_app_type] => B1 [patent_app_number] => 09/697581 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 1467 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/757/06757801.pdf [firstpage_image] =>[orig_patent_app_number] => 09697581 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697581
Method to modify that an operation needs to be done on a file system Oct 25, 2000 Issued
Array ( [id] => 1169618 [patent_doc_number] => 06763433 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-07-13 [patent_title] => 'High performance cache intervention mechanism for symmetric multiprocessor systems' [patent_app_type] => B1 [patent_app_number] => 09/696910 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4572 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/763/06763433.pdf [firstpage_image] =>[orig_patent_app_number] => 09696910 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/696910
High performance cache intervention mechanism for symmetric multiprocessor systems Oct 25, 2000 Issued
Array ( [id] => 1183583 [patent_doc_number] => 06751719 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-06-15 [patent_title] => 'Method and an apparatus to dynamically order features and to resolve conflicts in a multiple-layer logical volume management environment' [patent_app_type] => B1 [patent_app_number] => 09/697449 [patent_app_country] => US [patent_app_date] => 2000-10-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 4629 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 13 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/751/06751719.pdf [firstpage_image] =>[orig_patent_app_number] => 09697449 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/697449
Method and an apparatus to dynamically order features and to resolve conflicts in a multiple-layer logical volume management environment Oct 25, 2000 Issued
09/695970 Device capable of changing codes of micro-controller Oct 25, 2000 Abandoned
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