Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1196939 [patent_doc_number] => 06732229 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-04 [patent_title] => 'Method and apparatus for memory redundancy with no critical delay-path' [patent_app_type] => B1 [patent_app_number] => 09/503751 [patent_app_country] => US [patent_app_date] => 2000-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 13962 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/732/06732229.pdf [firstpage_image] =>[orig_patent_app_number] => 09503751 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/503751
Method and apparatus for memory redundancy with no critical delay-path Feb 13, 2000 Issued
Array ( [id] => 1406760 [patent_doc_number] => 06560683 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-06 [patent_title] => 'Fibre channel data storage system having improved rear-end I/O adapted hub' [patent_app_type] => B1 [patent_app_number] => 09/474500 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 10443 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 344 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/560/06560683.pdf [firstpage_image] =>[orig_patent_app_number] => 09474500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474500
Fibre channel data storage system having improved rear-end I/O adapted hub Dec 28, 1999 Issued
Array ( [id] => 1325154 [patent_doc_number] => 06615315 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-02 [patent_title] => 'Fibre channel data storage system having improved fro-end I/O adapted hub' [patent_app_type] => B1 [patent_app_number] => 09/474384 [patent_app_country] => US [patent_app_date] => 1999-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 26 [patent_no_of_words] => 10490 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 233 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/615/06615315.pdf [firstpage_image] =>[orig_patent_app_number] => 09474384 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/474384
Fibre channel data storage system having improved fro-end I/O adapted hub Dec 28, 1999 Issued
Array ( [id] => 7642390 [patent_doc_number] => 06430656 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-06 [patent_title] => 'Cache and management method using combined software and hardware congruence class selectors' [patent_app_type] => B1 [patent_app_number] => 09/435949 [patent_app_country] => US [patent_app_date] => 1999-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4071 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 5 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/430/06430656.pdf [firstpage_image] =>[orig_patent_app_number] => 09435949 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/435949
Cache and management method using combined software and hardware congruence class selectors Nov 8, 1999 Issued
Array ( [id] => 1248916 [patent_doc_number] => 06678832 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Memory controller for controlling an integrated memory undergoing logical state transitions' [patent_app_type] => B1 [patent_app_number] => 09/430538 [patent_app_country] => US [patent_app_date] => 1999-10-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3251 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 173 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678832.pdf [firstpage_image] =>[orig_patent_app_number] => 09430538 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/430538
Memory controller for controlling an integrated memory undergoing logical state transitions Oct 28, 1999 Issued
Array ( [id] => 1248879 [patent_doc_number] => 06678813 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Dynamically adaptive buffer mechanism' [patent_app_type] => B1 [patent_app_number] => 09/428874 [patent_app_country] => US [patent_app_date] => 1999-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4443 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678813.pdf [firstpage_image] =>[orig_patent_app_number] => 09428874 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/428874
Dynamically adaptive buffer mechanism Oct 27, 1999 Issued
Array ( [id] => 1149667 [patent_doc_number] => 06782465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-08-24 [patent_title] => 'Linked list DMA descriptor architecture' [patent_app_type] => B1 [patent_app_number] => 09/421745 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 1880 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/782/06782465.pdf [firstpage_image] =>[orig_patent_app_number] => 09421745 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421745
Linked list DMA descriptor architecture Oct 19, 1999 Issued
Array ( [id] => 1385807 [patent_doc_number] => 06571313 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Memory for information search through prefix analysis, in particular for building routing tables for nodes of high speed communication networks, such as the internet network' [patent_app_type] => B1 [patent_app_number] => 09/421505 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 17 [patent_no_of_words] => 7208 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 300 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571313.pdf [firstpage_image] =>[orig_patent_app_number] => 09421505 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421505
Memory for information search through prefix analysis, in particular for building routing tables for nodes of high speed communication networks, such as the internet network Oct 19, 1999 Issued
Array ( [id] => 7633094 [patent_doc_number] => 06658526 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-12-02 [patent_title] => 'Network attached virtual data storage subsystem' [patent_app_type] => B2 [patent_app_number] => 09/421916 [patent_app_country] => US [patent_app_date] => 1999-10-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 4 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658526.pdf [firstpage_image] =>[orig_patent_app_number] => 09421916 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/421916
Network attached virtual data storage subsystem Oct 19, 1999 Issued
Array ( [id] => 1186335 [patent_doc_number] => 06742078 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-05-25 [patent_title] => 'Management, data link structure and calculating method for flash memory' [patent_app_type] => B1 [patent_app_number] => 09/412323 [patent_app_country] => US [patent_app_date] => 1999-10-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 4466 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/742/06742078.pdf [firstpage_image] =>[orig_patent_app_number] => 09412323 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/412323
Management, data link structure and calculating method for flash memory Oct 4, 1999 Issued
Array ( [id] => 1595800 [patent_doc_number] => 06484218 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-19 [patent_title] => 'Method for improving direct memory access performance' [patent_app_type] => B1 [patent_app_number] => 09/411444 [patent_app_country] => US [patent_app_date] => 1999-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4191 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/484/06484218.pdf [firstpage_image] =>[orig_patent_app_number] => 09411444 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/411444
Method for improving direct memory access performance Sep 30, 1999 Issued
Array ( [id] => 1243088 [patent_doc_number] => 06684287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-27 [patent_title] => 'Turning read/write performance for disk drives with very high track density' [patent_app_type] => B1 [patent_app_number] => 09/400921 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4937 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 506 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/684/06684287.pdf [firstpage_image] =>[orig_patent_app_number] => 09400921 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400921
Turning read/write performance for disk drives with very high track density Sep 20, 1999 Issued
Array ( [id] => 7610018 [patent_doc_number] => 06842841 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2005-01-11 [patent_title] => 'Method and system for dynamically selecting tape drives to connect with host computers' [patent_app_type] => utility [patent_app_number] => 09/400500 [patent_app_country] => US [patent_app_date] => 1999-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3692 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 177 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/842/06842841.pdf [firstpage_image] =>[orig_patent_app_number] => 09400500 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/400500
Method and system for dynamically selecting tape drives to connect with host computers Sep 20, 1999 Issued
Array ( [id] => 1100382 [patent_doc_number] => 06823429 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-11-23 [patent_title] => 'Memory controller for controlling memory accesses across networks in distributed shared memory processing systems' [patent_app_type] => B1 [patent_app_number] => 09/394564 [patent_app_country] => US [patent_app_date] => 1999-09-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 41 [patent_figures_cnt] => 54 [patent_no_of_words] => 25999 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/823/06823429.pdf [firstpage_image] =>[orig_patent_app_number] => 09394564 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/394564
Memory controller for controlling memory accesses across networks in distributed shared memory processing systems Sep 9, 1999 Issued
Array ( [id] => 1587421 [patent_doc_number] => 06425058 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-23 [patent_title] => 'Cache management mechanism to enable information-type dependent cache policies' [patent_app_type] => B1 [patent_app_number] => 09/390186 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4947 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/425/06425058.pdf [firstpage_image] =>[orig_patent_app_number] => 09390186 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390186
Cache management mechanism to enable information-type dependent cache policies Sep 6, 1999 Issued
Array ( [id] => 1604483 [patent_doc_number] => 06434669 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of cache management to dynamically update information-type dependent cache policies' [patent_app_type] => B1 [patent_app_number] => 09/390189 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4977 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 137 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434669.pdf [firstpage_image] =>[orig_patent_app_number] => 09390189 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390189
Method of cache management to dynamically update information-type dependent cache policies Sep 6, 1999 Issued
Array ( [id] => 1604482 [patent_doc_number] => 06434668 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-08-13 [patent_title] => 'Method of cache management to store information in particular regions of the cache according to information-type' [patent_app_type] => B1 [patent_app_number] => 09/390187 [patent_app_country] => US [patent_app_date] => 1999-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5009 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/434/06434668.pdf [firstpage_image] =>[orig_patent_app_number] => 09390187 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/390187
Method of cache management to store information in particular regions of the cache according to information-type Sep 6, 1999 Issued
Array ( [id] => 7962231 [patent_doc_number] => 06681314 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-20 [patent_title] => 'FIFO memory device suitable for data transfer apparatuses with different data bus widths and method for controlling the same' [patent_app_type] => B1 [patent_app_number] => 09/387450 [patent_app_country] => US [patent_app_date] => 1999-09-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 18 [patent_no_of_words] => 7134 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/681/06681314.pdf [firstpage_image] =>[orig_patent_app_number] => 09387450 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/387450
FIFO memory device suitable for data transfer apparatuses with different data bus widths and method for controlling the same Aug 31, 1999 Issued
Array ( [id] => 1540579 [patent_doc_number] => 06490666 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Buffering data in a hierarchical data storage environment' [patent_app_type] => B1 [patent_app_number] => 09/378050 [patent_app_country] => US [patent_app_date] => 1999-08-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6861 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490666.pdf [firstpage_image] =>[orig_patent_app_number] => 09378050 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/378050
Buffering data in a hierarchical data storage environment Aug 19, 1999 Issued
Array ( [id] => 1221729 [patent_doc_number] => 06708261 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-03-16 [patent_title] => 'Multi-stage data buffers having efficient data transfer characteristics and methods of operating same' [patent_app_type] => B1 [patent_app_number] => 09/377428 [patent_app_country] => US [patent_app_date] => 1999-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 2013 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/708/06708261.pdf [firstpage_image] =>[orig_patent_app_number] => 09377428 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/377428
Multi-stage data buffers having efficient data transfer characteristics and methods of operating same Aug 18, 1999 Issued
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