Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1497856 [patent_doc_number] => 06343355 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Sequence controller capable of executing different kinds of processing at respective periods' [patent_app_type] => B1 [patent_app_number] => 09/261462 [patent_app_country] => US [patent_app_date] => 1999-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 4621 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343355.pdf [firstpage_image] =>[orig_patent_app_number] => 09261462 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/261462
Sequence controller capable of executing different kinds of processing at respective periods Feb 23, 1999 Issued
09/256746 MEMORY REDUNDANCY SCHEME HAVING NO CRITICAL PATH Feb 23, 1999 Abandoned
Array ( [id] => 1456795 [patent_doc_number] => 06457114 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-09-24 [patent_title] => 'Asynchronous memory interface for a video processor with a 2N sized buffer and N1 wide bit gray coded counters' [patent_app_type] => B1 [patent_app_number] => 09/255223 [patent_app_country] => US [patent_app_date] => 1999-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 18 [patent_no_of_words] => 24350 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/457/06457114.pdf [firstpage_image] =>[orig_patent_app_number] => 09255223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/255223
Asynchronous memory interface for a video processor with a 2N sized buffer and N1 wide bit gray coded counters Feb 21, 1999 Issued
Array ( [id] => 1466139 [patent_doc_number] => 06393511 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-05-21 [patent_title] => 'Multi-track density direct access storage device' [patent_app_type] => B1 [patent_app_number] => 09/246513 [patent_app_country] => US [patent_app_date] => 1999-02-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4408 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/393/06393511.pdf [firstpage_image] =>[orig_patent_app_number] => 09246513 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/246513
Multi-track density direct access storage device Feb 8, 1999 Issued
Array ( [id] => 7080114 [patent_doc_number] => 20010042177 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-15 [patent_title] => 'PROCESSOR AND SYSTEM FOR CONTROLLING SHARED ACCESS TO A MEMORY' [patent_app_type] => new [patent_app_number] => 09/169715 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2626 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0042/20010042177.pdf [firstpage_image] =>[orig_patent_app_number] => 09169715 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169715
Processor and system for controlling shared access to a memory Oct 8, 1998 Issued
Array ( [id] => 1357096 [patent_doc_number] => 06591347 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-07-08 [patent_title] => 'Dynamic replacement technique in a shared cache' [patent_app_type] => B2 [patent_app_number] => 09/169312 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5147 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591347.pdf [firstpage_image] =>[orig_patent_app_number] => 09169312 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169312
Dynamic replacement technique in a shared cache Oct 8, 1998 Issued
Array ( [id] => 1438660 [patent_doc_number] => 06356975 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Apparatus and method for pipelined memory operations' [patent_app_type] => B1 [patent_app_number] => 09/169526 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 37 [patent_figures_cnt] => 37 [patent_no_of_words] => 13136 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356975.pdf [firstpage_image] =>[orig_patent_app_number] => 09169526 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169526
Apparatus and method for pipelined memory operations Oct 8, 1998 Issued
Array ( [id] => 6531710 [patent_doc_number] => 20020026560 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2002-02-28 [patent_title] => 'LOAD BALANCING COOPERATING CACHE SERVERS BY SHIFTING FORWARDED REQUEST' [patent_app_type] => new [patent_app_number] => 09/169223 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 5736 [patent_no_of_claims] => 97 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 61 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0026/20020026560.pdf [firstpage_image] =>[orig_patent_app_number] => 09169223 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169223
Load balancing cooperating cache servers by shifting forwarded request Oct 8, 1998 Issued
Array ( [id] => 1557509 [patent_doc_number] => 06401167 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-06-04 [patent_title] => 'High performance cost optimized memory' [patent_app_type] => B1 [patent_app_number] => 09/169206 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 44 [patent_figures_cnt] => 50 [patent_no_of_words] => 9656 [patent_no_of_claims] => 67 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/401/06401167.pdf [firstpage_image] =>[orig_patent_app_number] => 09169206 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169206
High performance cost optimized memory Oct 8, 1998 Issued
Array ( [id] => 7066666 [patent_doc_number] => 20010044884 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'PROCESSOR AND SYSTEM FOR CONTROLLING SHARED ACCESS TO A MEMORY' [patent_app_type] => new [patent_app_number] => 09/169402 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3610 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044884.pdf [firstpage_image] =>[orig_patent_app_number] => 09169402 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169402
Processor and system for controlling shared access to a memory Oct 8, 1998 Issued
Array ( [id] => 1497843 [patent_doc_number] => 06343352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-01-29 [patent_title] => 'Method and apparatus for two step memory write operations' [patent_app_type] => B1 [patent_app_number] => 09/169736 [patent_app_country] => US [patent_app_date] => 1998-10-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 16255 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/343/06343352.pdf [firstpage_image] =>[orig_patent_app_number] => 09169736 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/169736
Method and apparatus for two step memory write operations Oct 8, 1998 Issued
Array ( [id] => 1377165 [patent_doc_number] => 06578127 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Memory devices' [patent_app_type] => B1 [patent_app_number] => 09/164342 [patent_app_country] => US [patent_app_date] => 1998-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2626 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578127.pdf [firstpage_image] =>[orig_patent_app_number] => 09164342 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/164342
Memory devices Sep 30, 1998 Issued
Array ( [id] => 4280955 [patent_doc_number] => 06260124 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'System and method for dynamically resynchronizing backup data' [patent_app_type] => 1 [patent_app_number] => 9/134543 [patent_app_country] => US [patent_app_date] => 1998-08-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5091 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 377 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260124.pdf [firstpage_image] =>[orig_patent_app_number] => 134543 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/134543
System and method for dynamically resynchronizing backup data Aug 12, 1998 Issued
Array ( [id] => 4310016 [patent_doc_number] => 06212595 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-03 [patent_title] => 'Computer program product for fencing a member of a group of processes in a distributed processing environment' [patent_app_type] => 1 [patent_app_number] => 9/124672 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5412 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 456 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/212/06212595.pdf [firstpage_image] =>[orig_patent_app_number] => 124672 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124672
Computer program product for fencing a member of a group of processes in a distributed processing environment Jul 28, 1998 Issued
Array ( [id] => 1508990 [patent_doc_number] => 06467017 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-15 [patent_title] => 'Programmable logic device having embedded dual-port random access memory configurable as single-port memory' [patent_app_type] => B1 [patent_app_number] => 09/124649 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4315 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/467/06467017.pdf [firstpage_image] =>[orig_patent_app_number] => 09124649 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124649
Programmable logic device having embedded dual-port random access memory configurable as single-port memory Jul 28, 1998 Issued
Array ( [id] => 4379483 [patent_doc_number] => 06192443 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-02-20 [patent_title] => 'Apparatus for fencing a member of a group of processes in a distributed processing environment' [patent_app_type] => 1 [patent_app_number] => 9/124394 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5393 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 442 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/192/06192443.pdf [firstpage_image] =>[orig_patent_app_number] => 124394 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124394
Apparatus for fencing a member of a group of processes in a distributed processing environment Jul 28, 1998 Issued
Array ( [id] => 4279664 [patent_doc_number] => 06205510 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-03-20 [patent_title] => 'Method for fencing a member of a group of processes in a distributed processing environment' [patent_app_type] => 1 [patent_app_number] => 9/124677 [patent_app_country] => US [patent_app_date] => 1998-07-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5404 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/205/06205510.pdf [firstpage_image] =>[orig_patent_app_number] => 124677 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/124677
Method for fencing a member of a group of processes in a distributed processing environment Jul 28, 1998 Issued
Array ( [id] => 1400939 [patent_doc_number] => 06564290 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-13 [patent_title] => 'Data carrier archiving and control system' [patent_app_type] => B1 [patent_app_number] => 09/123628 [patent_app_country] => US [patent_app_date] => 1998-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4886 [patent_no_of_claims] => 44 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 212 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/564/06564290.pdf [firstpage_image] =>[orig_patent_app_number] => 09123628 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/123628
Data carrier archiving and control system Jul 27, 1998 Issued
Array ( [id] => 1459998 [patent_doc_number] => 06463502 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-10-08 [patent_title] => 'Backup copying of data to a tape unit with a cache memory' [patent_app_type] => B1 [patent_app_number] => 09/068162 [patent_app_country] => US [patent_app_date] => 1998-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 2493 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 179 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/463/06463502.pdf [firstpage_image] =>[orig_patent_app_number] => 09068162 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/068162
Backup copying of data to a tape unit with a cache memory Jul 23, 1998 Issued
Array ( [id] => 4337024 [patent_doc_number] => 06249839 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-06-19 [patent_title] => 'Color palette RAM and D/A converter' [patent_app_type] => 1 [patent_app_number] => 9/092907 [patent_app_country] => US [patent_app_date] => 1998-06-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 28 [patent_no_of_words] => 18838 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/249/06249839.pdf [firstpage_image] =>[orig_patent_app_number] => 092907 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/092907
Color palette RAM and D/A converter Jun 7, 1998 Issued
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