Anthony J Green

Array ( [id] => 4208721 [patent_doc_number] => 06154808 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Method and apparatus for controlling data erase operations of a non-volatile memory device' [patent_app_type] => 1 [patent_app_number] => 9/081023 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 18 [patent_no_of_words] => 3200 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154808.pdf [firstpage_image] =>[orig_patent_app_number] => 081023 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374579 [patent_doc_number] => 06170035 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Dynamic random access memory (DRAM) having variable configuration for data processing system and corresponding expansion support for the interleaved-block configuration thereof' [patent_app_type] => 1 [patent_app_number] => 9/080991 [patent_app_country] => US [patent_app_date] => 1998-05-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 6922 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170035.pdf [firstpage_image] =>[orig_patent_app_number] => 080991 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1549590 [patent_doc_number] => 06374336 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-04-16 [patent_title] => 'Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner' [patent_app_type] => B1 [patent_app_number] => 09/054761 [patent_app_country] => US [patent_app_date] => 1998-04-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 27 [patent_no_of_words] => 19078 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/374/06374336.pdf [firstpage_image] =>[orig_patent_app_number] => 09054761 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4238894 [patent_doc_number] => 06088763 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and apparatus for translating an effective address to a real address within a cache memory' [patent_app_type] => 1 [patent_app_number] => 9/039516 [patent_app_country] => US [patent_app_date] => 1998-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3079 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 205 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088763.pdf [firstpage_image] =>[orig_patent_app_number] => 039516 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4162344 [patent_doc_number] => 06032231 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-29 [patent_title] => 'Multiprocessor with split transaction bus architecture providing cache tag and address compare for sending retry direction to other bus module upon a match of subsequent address bus cycles to content of cache tag' [patent_app_type] => 1 [patent_app_number] => 9/040193 [patent_app_country] => US [patent_app_date] => 1998-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 5 [patent_no_of_words] => 5542 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/032/06032231.pdf [firstpage_image] =>[orig_patent_app_number] => 040193 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1418797 [patent_doc_number] => 06546467 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-04-08 [patent_title] => 'Cache coherency mechanism using an operation to be executed on the contents of a location in a cache specifying an address in main memory' [patent_app_type] => B2 [patent_app_number] => 09/033134 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 6386 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/546/06546467.pdf [firstpage_image] =>[orig_patent_app_number] => 09033134 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4202386 [patent_doc_number] => 06094706 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Caching in a data processing system using the pigeon hole principle' [patent_app_type] => 1 [patent_app_number] => 9/033326 [patent_app_country] => US [patent_app_date] => 1998-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7621 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 199 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094706.pdf [firstpage_image] =>[orig_patent_app_number] => 033326 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4171487 [patent_doc_number] => 06125428 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Apparatus for reproducing multimedia data, method for reproducing multimedia data, and record media containing multimedia data reproduction program' [patent_app_type] => 1 [patent_app_number] => 9/028486 [patent_app_country] => US [patent_app_date] => 1998-02-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 32 [patent_no_of_words] => 21685 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 521 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125428.pdf [firstpage_image] =>[orig_patent_app_number] => 028486 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4177208 [patent_doc_number] => 06105109 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'System speed loading of a writable cache code array' [patent_app_type] => 1 [patent_app_number] => 9/026327 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3023 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105109.pdf [firstpage_image] =>[orig_patent_app_number] => 026327 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4426628 [patent_doc_number] => 06178486 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-23 [patent_title] => 'Time allocation shared memory arbitration for disk drive controller' [patent_app_type] => 1 [patent_app_number] => 9/026472 [patent_app_country] => US [patent_app_date] => 1998-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 5599 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/178/06178486.pdf [firstpage_image] =>[orig_patent_app_number] => 026472 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524923 [patent_doc_number] => 06415373 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'Computer system and process for transferring multiple high bandwidth streams of data between multiple storage units and multiple applications in a scalable and reliable manner' [patent_app_type] => B1 [patent_app_number] => 09/006070 [patent_app_country] => US [patent_app_date] => 1998-01-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 23 [patent_no_of_words] => 17131 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415373.pdf [firstpage_image] =>[orig_patent_app_number] => 09006070 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4422356 [patent_doc_number] => 06173360 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Apparatus and method for allowing existing ECKD MVS DASD using an ESCON interface to be used by an open storage using SCSI-type interface' [patent_app_type] => 1 [patent_app_number] => 9/005052 [patent_app_country] => US [patent_app_date] => 1998-01-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5236 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173360.pdf [firstpage_image] =>[orig_patent_app_number] => 005052 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4280844 [patent_doc_number] => 06260117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency' [patent_app_type] => 1 [patent_app_number] => 8/999961 [patent_app_country] => US [patent_app_date] => 1998-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 8220 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260117.pdf [firstpage_image] =>[orig_patent_app_number] => 999961 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1524896 [patent_doc_number] => 06415364 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-07-02 [patent_title] => 'High-speed memory storage unit for a multiprocessor system having integrated directory and data storage subsystems' [patent_app_type] => B1 [patent_app_number] => 09/001588 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 11723 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 373 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/415/06415364.pdf [firstpage_image] =>[orig_patent_app_number] => 09001588 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1438695 [patent_doc_number] => 06356991 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-12 [patent_title] => 'Programmable address translation system' [patent_app_type] => B1 [patent_app_number] => 09/001390 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7758 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/356/06356991.pdf [firstpage_image] =>[orig_patent_app_number] => 09001390 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1361399 [patent_doc_number] => 06587931 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-01 [patent_title] => 'Directory-based cache coherency system supporting multiple instruction processor and input/output caches' [patent_app_type] => B1 [patent_app_number] => 09/001598 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 15325 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 148 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/587/06587931.pdf [firstpage_image] =>[orig_patent_app_number] => 09001598 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4312272 [patent_doc_number] => 06237071 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Multiaccess circuit including arbitration capabilities to effectively perform pipeline and suspend operations according to its priority' [patent_app_type] => 1 [patent_app_number] => 9/001475 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 38 [patent_no_of_words] => 4097 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 210 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237071.pdf [firstpage_image] =>[orig_patent_app_number] => 001475 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 1533116 [patent_doc_number] => 06480927 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-11-12 [patent_title] => 'High-performance modular memory system with crossbar connections' [patent_app_type] => B1 [patent_app_number] => 09/001592 [patent_app_country] => US [patent_app_date] => 1997-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 17502 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/480/06480927.pdf [firstpage_image] =>[orig_patent_app_number] => 09001592 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4374712 [patent_doc_number] => 06170044 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-02 [patent_title] => 'Systems and methods for synchronizing redundant controllers with minimal control disruption' [patent_app_type] => 1 [patent_app_number] => 8/993336 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6640 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/170/06170044.pdf [firstpage_image] =>[orig_patent_app_number] => 993336 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 4155881 [patent_doc_number] => 06122709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Cache with reduced tag information storage' [patent_app_type] => 1 [patent_app_number] => 8/994376 [patent_app_country] => US [patent_app_date] => 1997-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 6411 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122709.pdf [firstpage_image] =>[orig_patent_app_number] => 994376 [rel_patent_id] =>[rel_patent_doc_number] =>)