Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4203664 [patent_doc_number] => 06161169 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Method and apparatus for asynchronously reading and writing data streams into a storage device using shared memory buffers and semaphores to synchronize interprocess communications' [patent_app_type] => 1 [patent_app_number] => 8/917633 [patent_app_country] => US [patent_app_date] => 1997-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2667 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161169.pdf [firstpage_image] =>[orig_patent_app_number] => 917633 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/917633
Method and apparatus for asynchronously reading and writing data streams into a storage device using shared memory buffers and semaphores to synchronize interprocess communications Aug 21, 1997 Issued
Array ( [id] => 4376733 [patent_doc_number] => 06219771 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-04-17 [patent_title] => 'Data storage apparatus with improved security process and partition allocation functions' [patent_app_type] => 1 [patent_app_number] => 8/912791 [patent_app_country] => US [patent_app_date] => 1997-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4462 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/219/06219771.pdf [firstpage_image] =>[orig_patent_app_number] => 912791 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/912791
Data storage apparatus with improved security process and partition allocation functions Aug 17, 1997 Issued
Array ( [id] => 4155866 [patent_doc_number] => 06122708 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-19 [patent_title] => 'Data cache for use with streaming data' [patent_app_type] => 1 [patent_app_number] => 8/911709 [patent_app_country] => US [patent_app_date] => 1997-08-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5147 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 200 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/122/06122708.pdf [firstpage_image] =>[orig_patent_app_number] => 911709 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/911709
Data cache for use with streaming data Aug 14, 1997 Issued
Array ( [id] => 4255138 [patent_doc_number] => 06119211 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-12 [patent_title] => 'Circuit for controlling writing data into memory and allowing concurrent reset generation and writing data operation' [patent_app_type] => 1 [patent_app_number] => 8/910021 [patent_app_country] => US [patent_app_date] => 1997-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 13 [patent_no_of_words] => 5992 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 294 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/119/06119211.pdf [firstpage_image] =>[orig_patent_app_number] => 910021 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/910021
Circuit for controlling writing data into memory and allowing concurrent reset generation and writing data operation Aug 11, 1997 Issued
Array ( [id] => 4122097 [patent_doc_number] => 06052767 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Semiconductor device having redundant memory cell arrays and serially accessing addresses' [patent_app_type] => 1 [patent_app_number] => 8/903375 [patent_app_country] => US [patent_app_date] => 1997-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4213 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 237 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052767.pdf [firstpage_image] =>[orig_patent_app_number] => 903375 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/903375
Semiconductor device having redundant memory cell arrays and serially accessing addresses Jul 29, 1997 Issued
Array ( [id] => 4238909 [patent_doc_number] => 06088764 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Method and apparatus for reducing space allocation failures in storage management systems' [patent_app_type] => 1 [patent_app_number] => 8/892246 [patent_app_country] => US [patent_app_date] => 1997-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 0 [patent_no_of_words] => 3654 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 310 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088764.pdf [firstpage_image] =>[orig_patent_app_number] => 892246 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/892246
Method and apparatus for reducing space allocation failures in storage management systems Jul 13, 1997 Issued
Array ( [id] => 3970525 [patent_doc_number] => 05991855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-23 [patent_title] => 'Low latency memory read with concurrent pipe lined snoops' [patent_app_type] => 1 [patent_app_number] => 8/887039 [patent_app_country] => US [patent_app_date] => 1997-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 8658 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/991/05991855.pdf [firstpage_image] =>[orig_patent_app_number] => 887039 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/887039
Low latency memory read with concurrent pipe lined snoops Jul 1, 1997 Issued
Array ( [id] => 4202431 [patent_doc_number] => 06094709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Cache coherence for lazy entry consistency in lockup-free caches' [patent_app_type] => 1 [patent_app_number] => 8/886222 [patent_app_country] => US [patent_app_date] => 1997-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 3660 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094709.pdf [firstpage_image] =>[orig_patent_app_number] => 886222 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/886222
Cache coherence for lazy entry consistency in lockup-free caches Jun 30, 1997 Issued
Array ( [id] => 3970992 [patent_doc_number] => 06000004 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Nonvolatile semiconductor memory device with write protect data settings for disabling erase from and write into a block, and erase and re-erase settings for enabling write into and erase from a block' [patent_app_type] => 1 [patent_app_number] => 8/884981 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 13887 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000004.pdf [firstpage_image] =>[orig_patent_app_number] => 884981 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/884981
Nonvolatile semiconductor memory device with write protect data settings for disabling erase from and write into a block, and erase and re-erase settings for enabling write into and erase from a block Jun 29, 1997 Issued
Array ( [id] => 6890776 [patent_doc_number] => 20010008007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-07-12 [patent_title] => 'COMMAND INSERTION AND REORDERING AT THE STORAGE CONTROLLER' [patent_app_type] => new-utility [patent_app_number] => 08/885380 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3053 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0008/20010008007.pdf [firstpage_image] =>[orig_patent_app_number] => 08885380 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885380
Command insertion and reordering at the same storage controller Jun 29, 1997 Issued
Array ( [id] => 4177318 [patent_doc_number] => 06105117 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-15 [patent_title] => 'Source oriented data block relocation methodology and applications' [patent_app_type] => 1 [patent_app_number] => 8/885327 [patent_app_country] => US [patent_app_date] => 1997-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 16 [patent_no_of_words] => 4651 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/105/06105117.pdf [firstpage_image] =>[orig_patent_app_number] => 885327 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/885327
Source oriented data block relocation methodology and applications Jun 29, 1997 Issued
Array ( [id] => 1385980 [patent_doc_number] => 06571324 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system' [patent_app_type] => B1 [patent_app_number] => 08/883381 [patent_app_country] => US [patent_app_date] => 1997-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3165 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571324.pdf [firstpage_image] =>[orig_patent_app_number] => 08883381 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/883381
Warmswap of failed memory modules and data reconstruction in a mirrored writeback cache system Jun 25, 1997 Issued
Array ( [id] => 4208830 [patent_doc_number] => 06154815 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-11-28 [patent_title] => 'Non-blocking hierarchical cache throttle' [patent_app_type] => 1 [patent_app_number] => 8/881728 [patent_app_country] => US [patent_app_date] => 1997-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7820 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/154/06154815.pdf [firstpage_image] =>[orig_patent_app_number] => 881728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881728
Non-blocking hierarchical cache throttle Jun 24, 1997 Issued
Array ( [id] => 4304728 [patent_doc_number] => 06269426 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-31 [patent_title] => 'Method for operating a non-blocking hierarchical cache throttle' [patent_app_type] => 1 [patent_app_number] => 8/881724 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 7805 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 290 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/269/06269426.pdf [firstpage_image] =>[orig_patent_app_number] => 881724 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881724
Method for operating a non-blocking hierarchical cache throttle Jun 23, 1997 Issued
Array ( [id] => 1377046 [patent_doc_number] => 06578120 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-06-10 [patent_title] => 'Synchronization and resynchronization of loosely-coupled copy operations between a primary and a remote secondary DASD volume under concurrent updating' [patent_app_type] => B1 [patent_app_number] => 08/881118 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 10 [patent_no_of_words] => 6756 [patent_no_of_claims] => 27 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 273 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/578/06578120.pdf [firstpage_image] =>[orig_patent_app_number] => 08881118 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881118
Synchronization and resynchronization of loosely-coupled copy operations between a primary and a remote secondary DASD volume under concurrent updating Jun 23, 1997 Issued
Array ( [id] => 4103783 [patent_doc_number] => 06026472 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Method and apparatus for determining memory page access information in a non-uniform memory access computer system' [patent_app_type] => 1 [patent_app_number] => 8/881413 [patent_app_country] => US [patent_app_date] => 1997-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3132 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 215 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026472.pdf [firstpage_image] =>[orig_patent_app_number] => 881413 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881413
Method and apparatus for determining memory page access information in a non-uniform memory access computer system Jun 23, 1997 Issued
Array ( [id] => 1540556 [patent_doc_number] => 06490658 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-12-03 [patent_title] => 'Data prefetch technique using prefetch cache, micro-TLB, and history file' [patent_app_type] => B1 [patent_app_number] => 08/881013 [patent_app_country] => US [patent_app_date] => 1997-06-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5783 [patent_no_of_claims] => 34 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 71 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/490/06490658.pdf [firstpage_image] =>[orig_patent_app_number] => 08881013 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/881013
Data prefetch technique using prefetch cache, micro-TLB, and history file Jun 22, 1997 Issued
Array ( [id] => 4202459 [patent_doc_number] => 06094711 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-25 [patent_title] => 'Apparatus and method for reducing data bus pin count of an interface while substantially maintaining performance' [patent_app_type] => 1 [patent_app_number] => 8/877455 [patent_app_country] => US [patent_app_date] => 1997-06-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6127 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 286 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/094/06094711.pdf [firstpage_image] =>[orig_patent_app_number] => 877455 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/877455
Apparatus and method for reducing data bus pin count of an interface while substantially maintaining performance Jun 16, 1997 Issued
Array ( [id] => 4259849 [patent_doc_number] => 06092158 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Method and apparatus for arbitrating between command streams' [patent_app_type] => 1 [patent_app_number] => 8/874414 [patent_app_country] => US [patent_app_date] => 1997-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3673 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 83 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092158.pdf [firstpage_image] =>[orig_patent_app_number] => 874414 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/874414
Method and apparatus for arbitrating between command streams Jun 12, 1997 Issued
Array ( [id] => 4171546 [patent_doc_number] => 06125431 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-26 [patent_title] => 'Single-chip microcomputer using adjustable timing to fetch data from an external memory' [patent_app_type] => 1 [patent_app_number] => 8/871537 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2470 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 189 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/125/06125431.pdf [firstpage_image] =>[orig_patent_app_number] => 871537 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871537
Single-chip microcomputer using adjustable timing to fetch data from an external memory Jun 8, 1997 Issued
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