Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1248832 [patent_doc_number] => 06678790 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2004-01-13 [patent_title] => 'Microprocessor chip having a memory that is reconfigurable to function as on-chip main memory or an on-chip cache' [patent_app_type] => B1 [patent_app_number] => 08/871295 [patent_app_country] => US [patent_app_date] => 1997-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3714 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 251 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/678/06678790.pdf [firstpage_image] =>[orig_patent_app_number] => 08871295 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/871295
Microprocessor chip having a memory that is reconfigurable to function as on-chip main memory or an on-chip cache Jun 8, 1997 Issued
Array ( [id] => 4194981 [patent_doc_number] => 06085292 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Apparatus and method for providing non-blocking pipelined cache' [patent_app_type] => 1 [patent_app_number] => 8/870152 [patent_app_country] => US [patent_app_date] => 1997-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3318 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085292.pdf [firstpage_image] =>[orig_patent_app_number] => 870152 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/870152
Apparatus and method for providing non-blocking pipelined cache Jun 4, 1997 Issued
Array ( [id] => 4294681 [patent_doc_number] => 06324623 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-11-27 [patent_title] => 'Computing system for implementing a shared cache' [patent_app_type] => 1 [patent_app_number] => 8/866619 [patent_app_country] => US [patent_app_date] => 1997-05-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 12 [patent_no_of_words] => 6044 [patent_no_of_claims] => 64 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 175 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/324/06324623.pdf [firstpage_image] =>[orig_patent_app_number] => 866619 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/866619
Computing system for implementing a shared cache May 29, 1997 Issued
Array ( [id] => 4259713 [patent_doc_number] => 06092149 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-18 [patent_title] => 'Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses' [patent_app_type] => 1 [patent_app_number] => 8/864525 [patent_app_country] => US [patent_app_date] => 1997-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 66 [patent_figures_cnt] => 66 [patent_no_of_words] => 26611 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 409 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/092/06092149.pdf [firstpage_image] =>[orig_patent_app_number] => 864525 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/864525
Disk drive cache system using a dynamic priority sequential stream of data segments continuously adapted according to prefetched sequential random, and repeating types of accesses May 27, 1997 Issued
Array ( [id] => 1567459 [patent_doc_number] => 06363465 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2002-03-26 [patent_title] => 'Synchronous data transfer system and method with successive stage control allowing two more stages to simultaneous transfer' [patent_app_type] => B1 [patent_app_number] => 08/861232 [patent_app_country] => US [patent_app_date] => 1997-05-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 32 [patent_no_of_words] => 16984 [patent_no_of_claims] => 30 [patent_no_of_ind_claims] => 12 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/363/06363465.pdf [firstpage_image] =>[orig_patent_app_number] => 08861232 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/861232
Synchronous data transfer system and method with successive stage control allowing two more stages to simultaneous transfer May 20, 1997 Issued
Array ( [id] => 4179122 [patent_doc_number] => 06115789 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method and system for determining which memory locations have been accessed in a self timed cache architecture' [patent_app_type] => 1 [patent_app_number] => 8/845868 [patent_app_country] => US [patent_app_date] => 1997-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3100 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115789.pdf [firstpage_image] =>[orig_patent_app_number] => 845868 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/845868
Method and system for determining which memory locations have been accessed in a self timed cache architecture Apr 27, 1997 Issued
Array ( [id] => 4199050 [patent_doc_number] => 06038640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-14 [patent_title] => 'Computer module having removable remotely programmable non-volatile memory' [patent_app_type] => 1 [patent_app_number] => 8/847382 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2196 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/038/06038640.pdf [firstpage_image] =>[orig_patent_app_number] => 847382 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/847382
Computer module having removable remotely programmable non-volatile memory Apr 23, 1997 Issued
Array ( [id] => 3978279 [patent_doc_number] => 05937433 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Method of controlling hard disk cache to reduce power consumption of hard disk drive used in battery powered computer' [patent_app_type] => 1 [patent_app_number] => 8/842398 [patent_app_country] => US [patent_app_date] => 1997-04-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 4605 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 266 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937433.pdf [firstpage_image] =>[orig_patent_app_number] => 842398 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842398
Method of controlling hard disk cache to reduce power consumption of hard disk drive used in battery powered computer Apr 23, 1997 Issued
Array ( [id] => 4138554 [patent_doc_number] => 06073204 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-06-06 [patent_title] => 'Memory system having flexible architecture and method' [patent_app_type] => 1 [patent_app_number] => 8/839034 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 33 [patent_figures_cnt] => 44 [patent_no_of_words] => 21407 [patent_no_of_claims] => 122 [patent_no_of_ind_claims] => 16 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/073/06073204.pdf [firstpage_image] =>[orig_patent_app_number] => 839034 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839034
Memory system having flexible architecture and method Apr 22, 1997 Issued
Array ( [id] => 4179022 [patent_doc_number] => 06115782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method and apparatus for locating nodes in a carded heap using a card marking structure and a node advance value' [patent_app_type] => 1 [patent_app_number] => 8/842136 [patent_app_country] => US [patent_app_date] => 1997-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 32 [patent_no_of_words] => 17007 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 171 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115782.pdf [firstpage_image] =>[orig_patent_app_number] => 842136 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/842136
Method and apparatus for locating nodes in a carded heap using a card marking structure and a node advance value Apr 22, 1997 Issued
Array ( [id] => 4099911 [patent_doc_number] => 06055608 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-25 [patent_title] => 'Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system' [patent_app_type] => 1 [patent_app_number] => 8/839526 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3000 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/055/06055608.pdf [firstpage_image] =>[orig_patent_app_number] => 839526 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839526
Method and system for speculatively sourcing cache memory data within a multiprocessor data-processing system Apr 13, 1997 Issued
Array ( [id] => 4194922 [patent_doc_number] => 06085288 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-04 [patent_title] => 'Dual cache directories with respective queue independently executing its content and allowing staggered write operations' [patent_app_type] => 1 [patent_app_number] => 8/839556 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6060 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/085/06085288.pdf [firstpage_image] =>[orig_patent_app_number] => 839556 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839556
Dual cache directories with respective queue independently executing its content and allowing staggered write operations Apr 13, 1997 Issued
Array ( [id] => 3971145 [patent_doc_number] => 06000014 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-12-07 [patent_title] => 'Software-managed programmable congruence class caching mechanism' [patent_app_type] => 1 [patent_app_number] => 8/834490 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5806 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/000/06000014.pdf [firstpage_image] =>[orig_patent_app_number] => 834490 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834490
Software-managed programmable congruence class caching mechanism Apr 13, 1997 Issued
Array ( [id] => 4317978 [patent_doc_number] => 06182201 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-30 [patent_title] => 'Demand-based issuance of cache operations to a system bus' [patent_app_type] => 1 [patent_app_number] => 8/834116 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3946 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/182/06182201.pdf [firstpage_image] =>[orig_patent_app_number] => 834116 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834116
Demand-based issuance of cache operations to a system bus Apr 13, 1997 Issued
Array ( [id] => 4103751 [patent_doc_number] => 06026470 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-02-15 [patent_title] => 'Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels' [patent_app_type] => 1 [patent_app_number] => 8/839546 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5911 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 152 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/026/06026470.pdf [firstpage_image] =>[orig_patent_app_number] => 839546 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839546
Software-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels Apr 13, 1997 Issued
Array ( [id] => 3967284 [patent_doc_number] => 05983322 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Hardware-managed programmable congruence class caching mechanism' [patent_app_type] => 1 [patent_app_number] => 8/839560 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5856 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983322.pdf [firstpage_image] =>[orig_patent_app_number] => 839560 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839560
Hardware-managed programmable congruence class caching mechanism Apr 13, 1997 Issued
Array ( [id] => 4126723 [patent_doc_number] => 06058456 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-05-02 [patent_title] => 'Software-managed programmable unified/split caching mechanism for instructions and data' [patent_app_type] => 1 [patent_app_number] => 8/837515 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 5809 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/058/06058456.pdf [firstpage_image] =>[orig_patent_app_number] => 837515 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837515
Software-managed programmable unified/split caching mechanism for instructions and data Apr 13, 1997 Issued
Array ( [id] => 3973385 [patent_doc_number] => 05978888 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-02 [patent_title] => 'Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels' [patent_app_type] => 1 [patent_app_number] => 8/839550 [patent_app_country] => US [patent_app_date] => 1997-04-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5880 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/978/05978888.pdf [firstpage_image] =>[orig_patent_app_number] => 839550 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/839550
Hardware-managed programmable associativity caching mechanism monitoring cache misses to selectively implement multiple associativity levels Apr 13, 1997 Issued
Array ( [id] => 3969542 [patent_doc_number] => 05956755 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-09-21 [patent_title] => 'Sequential permutation apparatus for rearranging input data' [patent_app_type] => 1 [patent_app_number] => 8/834463 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 66 [patent_no_of_words] => 17468 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/956/05956755.pdf [firstpage_image] =>[orig_patent_app_number] => 834463 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/834463
Sequential permutation apparatus for rearranging input data Apr 10, 1997 Issued
Array ( [id] => 4118165 [patent_doc_number] => 06098146 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-01 [patent_title] => 'Intelligent backplane for collecting and reporting information in an SSA system' [patent_app_type] => 1 [patent_app_number] => 8/837181 [patent_app_country] => US [patent_app_date] => 1997-04-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 6378 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/098/06098146.pdf [firstpage_image] =>[orig_patent_app_number] => 837181 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/837181
Intelligent backplane for collecting and reporting information in an SSA system Apr 10, 1997 Issued
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