Search

Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4402161 [patent_doc_number] => 06279077 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Bus interface buffer control in a microprocessor' [patent_app_type] => 1 [patent_app_number] => 8/821874 [patent_app_country] => US [patent_app_date] => 1997-03-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 14 [patent_no_of_words] => 12167 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279077.pdf [firstpage_image] =>[orig_patent_app_number] => 821874 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/821874
Bus interface buffer control in a microprocessor Mar 20, 1997 Issued
08/815739 NETWORK ATTACHED VIRTUAL TAPE DATA STORAGE SUBSYSTEM Mar 11, 1997 Abandoned
Array ( [id] => 4203598 [patent_doc_number] => 06161165 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'High performance data path with XOR on the fly' [patent_app_type] => 1 [patent_app_number] => 8/815193 [patent_app_country] => US [patent_app_date] => 1997-03-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 7427 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161165.pdf [firstpage_image] =>[orig_patent_app_number] => 815193 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/815193
High performance data path with XOR on the fly Mar 10, 1997 Issued
Array ( [id] => 4324508 [patent_doc_number] => 06327640 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-12-04 [patent_title] => 'Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller' [patent_app_type] => 1 [patent_app_number] => 8/813728 [patent_app_country] => US [patent_app_date] => 1997-03-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 2776 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/327/06327640.pdf [firstpage_image] =>[orig_patent_app_number] => 813728 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/813728
Overlapping peripheral chip select space with DRAM on a microcontroller with an integrated DRAM controller Mar 6, 1997 Issued
Array ( [id] => 4177774 [patent_doc_number] => 06108757 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'Method for locking a shared resource in multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/808921 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4636 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108757.pdf [firstpage_image] =>[orig_patent_app_number] => 808921 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808921
Method for locking a shared resource in multiprocessor system Feb 27, 1997 Issued
Array ( [id] => 4177624 [patent_doc_number] => 06108748 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-08-22 [patent_title] => 'System and method for on-line, real time, data migration' [patent_app_type] => 1 [patent_app_number] => 8/807331 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 12207 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/108/06108748.pdf [firstpage_image] =>[orig_patent_app_number] => 807331 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/807331
System and method for on-line, real time, data migration Feb 27, 1997 Issued
Array ( [id] => 4422538 [patent_doc_number] => 06173375 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-01-09 [patent_title] => 'Method for accessing a shared resource in a multiprocessor system' [patent_app_type] => 1 [patent_app_number] => 8/808920 [patent_app_country] => US [patent_app_date] => 1997-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 4797 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/173/06173375.pdf [firstpage_image] =>[orig_patent_app_number] => 808920 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/808920
Method for accessing a shared resource in a multiprocessor system Feb 27, 1997 Issued
Array ( [id] => 3978265 [patent_doc_number] => 05937432 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-08-10 [patent_title] => 'Associative storage and associative storing method' [patent_app_type] => 1 [patent_app_number] => 8/806937 [patent_app_country] => US [patent_app_date] => 1997-02-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 6700 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/937/05937432.pdf [firstpage_image] =>[orig_patent_app_number] => 806937 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/806937
Associative storage and associative storing method Feb 25, 1997 Issued
Array ( [id] => 4179082 [patent_doc_number] => 06115786 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-09-05 [patent_title] => 'Method for controlling disk memory devices for use in video on demand system' [patent_app_type] => 1 [patent_app_number] => 8/802883 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 5019 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/115/06115786.pdf [firstpage_image] =>[orig_patent_app_number] => 802883 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/802883
Method for controlling disk memory devices for use in video on demand system Feb 18, 1997 Issued
Array ( [id] => 4236409 [patent_doc_number] => 06041388 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-03-21 [patent_title] => 'Circuit and method for controlling memory depth' [patent_app_type] => 1 [patent_app_number] => 8/804025 [patent_app_country] => US [patent_app_date] => 1997-02-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 5027 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/041/06041388.pdf [firstpage_image] =>[orig_patent_app_number] => 804025 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/804025
Circuit and method for controlling memory depth Feb 18, 1997 Issued
Array ( [id] => 3967106 [patent_doc_number] => 05983310 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-09 [patent_title] => 'Pin management of accelerator for interpretive environments' [patent_app_type] => 1 [patent_app_number] => 8/799192 [patent_app_country] => US [patent_app_date] => 1997-02-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 13494 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/983/05983310.pdf [firstpage_image] =>[orig_patent_app_number] => 799192 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/799192
Pin management of accelerator for interpretive environments Feb 12, 1997 Issued
Array ( [id] => 7066626 [patent_doc_number] => 20010044874 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2001-11-22 [patent_title] => 'MEMORY SYSTEM CAPABLE OF SUPPORTING DIFFERENT MEMORY DEVICES AND A MEMORY DEVICE USED THEREFOR' [patent_app_type] => new [patent_app_number] => 08/798950 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 6703 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0044/20010044874.pdf [firstpage_image] =>[orig_patent_app_number] => 08798950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798950
Memory system capable of supporting different memory devices and a memory device used therefor Feb 10, 1997 Issued
Array ( [id] => 4424758 [patent_doc_number] => 06230245 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-08 [patent_title] => 'Method and apparatus for generating a variable sequence of memory device command signals' [patent_app_type] => 1 [patent_app_number] => 8/798229 [patent_app_country] => US [patent_app_date] => 1997-02-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 12 [patent_no_of_words] => 6004 [patent_no_of_claims] => 60 [patent_no_of_ind_claims] => 10 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/230/06230245.pdf [firstpage_image] =>[orig_patent_app_number] => 798229 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/798229
Method and apparatus for generating a variable sequence of memory device command signals Feb 10, 1997 Issued
Array ( [id] => 4121968 [patent_doc_number] => 06052761 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-04-18 [patent_title] => 'Increment update in an SCI based system' [patent_app_type] => 1 [patent_app_number] => 8/792310 [patent_app_country] => US [patent_app_date] => 1997-01-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 23 [patent_no_of_words] => 4160 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/052/06052761.pdf [firstpage_image] =>[orig_patent_app_number] => 792310 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/792310
Increment update in an SCI based system Jan 30, 1997 Issued
08/765988 SHARED CACHE MEMORY DEVICE Jan 9, 1997 Abandoned
Array ( [id] => 4374074 [patent_doc_number] => 06292875 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-09-18 [patent_title] => 'Control device for storage device and method of accessing the storage device' [patent_app_type] => 1 [patent_app_number] => 8/781907 [patent_app_country] => US [patent_app_date] => 1996-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 26 [patent_no_of_words] => 10066 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 11 [patent_words_short_claim] => 198 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/292/06292875.pdf [firstpage_image] =>[orig_patent_app_number] => 781907 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/781907
Control device for storage device and method of accessing the storage device Dec 29, 1996 Issued
Array ( [id] => 4402067 [patent_doc_number] => 06279069 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-08-21 [patent_title] => 'Interface for flash EEPROM memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/773169 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 8451 [patent_no_of_claims] => 32 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/279/06279069.pdf [firstpage_image] =>[orig_patent_app_number] => 773169 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773169
Interface for flash EEPROM memory arrays Dec 25, 1996 Issued
Array ( [id] => 4280621 [patent_doc_number] => 06260102 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-07-10 [patent_title] => 'Interface for flash EEPROM memory arrays' [patent_app_type] => 1 [patent_app_number] => 8/773167 [patent_app_country] => US [patent_app_date] => 1996-12-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6755 [patent_no_of_claims] => 28 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/260/06260102.pdf [firstpage_image] =>[orig_patent_app_number] => 773167 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/773167
Interface for flash EEPROM memory arrays Dec 25, 1996 Issued
Array ( [id] => 1279488 [patent_doc_number] => 06654853 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-25 [patent_title] => 'Method of secondary to secondary data transfer with mirroring' [patent_app_type] => B1 [patent_app_number] => 08/772443 [patent_app_country] => US [patent_app_date] => 1996-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 9 [patent_no_of_words] => 3691 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 20 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/654/06654853.pdf [firstpage_image] =>[orig_patent_app_number] => 08772443 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/772443
Method of secondary to secondary data transfer with mirroring Dec 22, 1996 Issued
Array ( [id] => 4176790 [patent_doc_number] => 06157992 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-05 [patent_title] => 'Synchronous semiconductor memory having read data mask controlled output circuit' [patent_app_type] => 1 [patent_app_number] => 8/768089 [patent_app_country] => US [patent_app_date] => 1996-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 6861 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/157/06157992.pdf [firstpage_image] =>[orig_patent_app_number] => 768089 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/768089
Synchronous semiconductor memory having read data mask controlled output circuit Dec 15, 1996 Issued
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