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Anthony J Green

Examiner (ID: 130, Phone: (571)272-1367 , Office: P/1731 )

Most Active Art Unit
1731
Art Unit(s)
1754, 2899, 1108, 1793, 1731, 1755
Total Applications
4596
Issued Applications
3675
Pending Applications
315
Abandoned Applications
605

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 4060411 [patent_doc_number] => 05913229 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-15 [patent_title] => 'Buffer memory controller storing and extracting data of varying bit lengths' [patent_app_type] => 1 [patent_app_number] => 8/766461 [patent_app_country] => US [patent_app_date] => 1996-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 9 [patent_no_of_words] => 2108 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 163 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/913/05913229.pdf [firstpage_image] =>[orig_patent_app_number] => 766461 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/766461
Buffer memory controller storing and extracting data of varying bit lengths Dec 11, 1996 Issued
Array ( [id] => 4019885 [patent_doc_number] => 05860120 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-01-12 [patent_title] => 'Directory-based coherency system using two bits to maintain coherency on a dual ported memory system' [patent_app_type] => 1 [patent_app_number] => 8/763702 [patent_app_country] => US [patent_app_date] => 1996-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4207 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/860/05860120.pdf [firstpage_image] =>[orig_patent_app_number] => 763702 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/763702
Directory-based coherency system using two bits to maintain coherency on a dual ported memory system Dec 8, 1996 Issued
Array ( [id] => 4238979 [patent_doc_number] => 06088769 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-07-11 [patent_title] => 'Multiprocessor cache coherence directed by combined local and global tables' [patent_app_type] => 1 [patent_app_number] => 8/724628 [patent_app_country] => US [patent_app_date] => 1996-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 5932 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/088/06088769.pdf [firstpage_image] =>[orig_patent_app_number] => 724628 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724628
Multiprocessor cache coherence directed by combined local and global tables Sep 30, 1996 Issued
Array ( [id] => 4059105 [patent_doc_number] => 05909702 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-06-01 [patent_title] => 'Memory address translations for programs code execution/relocation' [patent_app_type] => 1 [patent_app_number] => 8/724610 [patent_app_country] => US [patent_app_date] => 1996-09-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2433 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/909/05909702.pdf [firstpage_image] =>[orig_patent_app_number] => 724610 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/724610
Memory address translations for programs code execution/relocation Sep 29, 1996 Issued
08/723294 AN AUTOMATED COALESCED READ WITH OPTIONAL SKIPPED HIT Sep 29, 1996 Abandoned
Array ( [id] => 4203586 [patent_doc_number] => 06161164 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2000-12-12 [patent_title] => 'Content addressable memory accessed by the sum of two operands' [patent_app_type] => 1 [patent_app_number] => 8/716817 [patent_app_country] => US [patent_app_date] => 1996-09-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 3068 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/161/06161164.pdf [firstpage_image] =>[orig_patent_app_number] => 716817 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/716817
Content addressable memory accessed by the sum of two operands Sep 15, 1996 Issued
Array ( [id] => 4057478 [patent_doc_number] => 05996054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-30 [patent_title] => 'Efficient virtualized mapping space for log device data storage system' [patent_app_type] => 1 [patent_app_number] => 8/711890 [patent_app_country] => US [patent_app_date] => 1996-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 16 [patent_no_of_words] => 18685 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 313 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/996/05996054.pdf [firstpage_image] =>[orig_patent_app_number] => 711890 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/711890
Efficient virtualized mapping space for log device data storage system Sep 11, 1996 Issued
Array ( [id] => 4312328 [patent_doc_number] => 06237074 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 2001-05-22 [patent_title] => 'Tagged prefetch and instruction decoder for variable length instruction set and method of operation' [patent_app_type] => 1 [patent_app_number] => 8/445563 [patent_app_country] => US [patent_app_date] => 1995-05-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 11213 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 146 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/237/06237074.pdf [firstpage_image] =>[orig_patent_app_number] => 445563 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/445563
Tagged prefetch and instruction decoder for variable length instruction set and method of operation May 25, 1995 Issued
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