Anthony J. Salata

Array ( [id] => 18943720 [patent_doc_number] => 20240038859 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-01 [patent_title] => METAL CAP FOR CONTACT RESISTANCE REDUCTION [patent_app_type] => utility [patent_app_number] => 18/379600 [patent_app_country] => US [patent_app_date] => 2023-10-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6105 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -13 [patent_words_short_claim] => 79 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18379600 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19806054 [patent_doc_number] => 20250071979 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-27 [patent_title] => MEMORY DEVICES HAVING VERTICAL TRANSISTORS IN PERIPHERAL CIRCUITS [patent_app_type] => utility [patent_app_number] => 18/477521 [patent_app_country] => US [patent_app_date] => 2023-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 14411 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18477521 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19858268 [patent_doc_number] => 12261119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-03-25 [patent_title] => Method for manufacturing semiconductor device with impurity doped oxide semiconductor layer [patent_app_type] => utility [patent_app_number] => 18/370916 [patent_app_country] => US [patent_app_date] => 2023-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 71 [patent_no_of_words] => 29062 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 122 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18370916 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19852971 [patent_doc_number] => 20250098322 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-20 [patent_title] => METAL INSULATOR METAL CAPACITOR (MIM CAPACITOR) [patent_app_type] => utility [patent_app_number] => 18/466871 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9921 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18466871 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18882868 [patent_doc_number] => 20240006237 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-01-04 [patent_title] => METHOD OF FORMING COPPER INTERCONNECT STRUCTURE WITH MANGANESE BARRIER LAYER [patent_app_type] => utility [patent_app_number] => 18/368355 [patent_app_country] => US [patent_app_date] => 2023-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4503 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18368355 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19023127 [patent_doc_number] => 20240079298 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => METAL COMPONENT [patent_app_type] => utility [patent_app_number] => 18/458668 [patent_app_country] => US [patent_app_date] => 2023-08-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3460 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 52 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18458668 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19023090 [patent_doc_number] => 20240079261 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => METHOD OF MANUFACTURING LAMINATED DEVICE CHIPS [patent_app_type] => utility [patent_app_number] => 18/457577 [patent_app_country] => US [patent_app_date] => 2023-08-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11052 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 218 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18457577 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19073401 [patent_doc_number] => 20240107827 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => DISPLAY PANEL, DISPLAY DEVICE, AND METHOD OF MANUFACTURING DISPLAY PANEL [patent_app_type] => utility [patent_app_number] => 18/236245 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 31492 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18236245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19023072 [patent_doc_number] => 20240079243 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-07 [patent_title] => PROCESSING METHOD OF WAFER [patent_app_type] => utility [patent_app_number] => 18/452772 [patent_app_country] => US [patent_app_date] => 2023-08-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6867 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -2 [patent_words_short_claim] => 260 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452772 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20548719 [patent_doc_number] => 12559498 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2026-02-24 [patent_title] => Organic compound, light absorption sensor, sensor-embedded display panel, and electronic device [patent_app_type] => utility [patent_app_number] => 18/452069 [patent_app_country] => US [patent_app_date] => 2023-08-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 22875 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 150 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18452069 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19788524 [patent_doc_number] => 20250062203 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-20 [patent_title] => SUBSTRATE(S) FOR AN INTEGRATED CIRCUIT (IC) PACKAGE EMPLOYING A CORE LAYER AND AN ADJACENT INSULATION LAYER(S) WITH AN EMBEDDED METAL STRUCTURE(S) POSITIONED FROM THE CORE LAYER [patent_app_type] => utility [patent_app_number] => 18/451354 [patent_app_country] => US [patent_app_date] => 2023-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10184 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18451354 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19071313 [patent_doc_number] => 20240105739 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-03-28 [patent_title] => ELECTRONIC DEVICE [patent_app_type] => utility [patent_app_number] => 18/450593 [patent_app_country] => US [patent_app_date] => 2023-08-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10779 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18450593 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19193508 [patent_doc_number] => 20240172421 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 18/233357 [patent_app_country] => US [patent_app_date] => 2023-08-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7766 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18233357 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18815021 [patent_doc_number] => 20230389359 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => DISPLAY DEVICE [patent_app_type] => utility [patent_app_number] => 18/447332 [patent_app_country] => US [patent_app_date] => 2023-08-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8457 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18447332 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18977309 [patent_doc_number] => 20240057401 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-02-15 [patent_title] => DISPLAY APPARATUS [patent_app_type] => utility [patent_app_number] => 18/229392 [patent_app_country] => US [patent_app_date] => 2023-08-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17939 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18229392 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18812940 [patent_doc_number] => 20230387277 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => GATED METAL-INSULATOR-SEMICONDUCTOR (MIS) TUNNEL DIODE HAVING NEGATIVE TRANSCONDUCTANCE [patent_app_type] => utility [patent_app_number] => 18/361758 [patent_app_country] => US [patent_app_date] => 2023-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10225 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18361758 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18812681 [patent_doc_number] => 20230387018 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-30 [patent_title] => GRAPHENE LAYER FOR REDUCED CONTACT RESISTANCE [patent_app_type] => utility [patent_app_number] => 18/359383 [patent_app_country] => US [patent_app_date] => 2023-07-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4577 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 55 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18359383 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 19191694 [patent_doc_number] => 20240170607 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2024-05-23 [patent_title] => SEMICONDUCTOR STRUCTURE [patent_app_type] => utility [patent_app_number] => 18/357433 [patent_app_country] => US [patent_app_date] => 2023-07-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4076 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18357433 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 18757775 [patent_doc_number] => 20230361238 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2023-11-09 [patent_title] => METHOD FOR MANUFACTURING MONOCRYSTALLINE SILICON WAFER CONTAINING ARCED SIDE, METHOD FOR MANUFACTURING MONOCRYSTALLINE SILICON CELL, AND PHOTOVOLTAIC MODULE [patent_app_type] => utility [patent_app_number] => 18/222377 [patent_app_country] => US [patent_app_date] => 2023-07-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4540 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 72 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18222377 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 20119560 [patent_doc_number] => 12369298 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-07-22 [patent_title] => Semiconductor device with etched landing pad surface and manufacturing method thereof [patent_app_type] => utility [patent_app_number] => 18/218212 [patent_app_country] => US [patent_app_date] => 2023-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 5477 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18218212 [rel_patent_id] =>[rel_patent_doc_number] =>)