Anthony L. Bacon

Array ( [id] => 12573933 [patent_doc_number] => 10020237 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2018-07-10 [patent_title] => Power semiconductor module and method for producing a power semiconductor module [patent_app_type] => utility [patent_app_number] => 14/925274 [patent_app_country] => US [patent_app_date] => 2015-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 8 [patent_no_of_words] => 4750 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14925274 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14252665 [patent_doc_number] => 10276540 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-04-30 [patent_title] => Chip packaging method and chip packaging structure [patent_app_type] => utility [patent_app_number] => 15/558341 [patent_app_country] => US [patent_app_date] => 2015-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 19 [patent_no_of_words] => 12074 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 255 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15558341 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11615529 [patent_doc_number] => 09653392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-16 [patent_title] => 'Metallic device having mobile element in a cavity of the BEOL of an integrated circuit' [patent_app_type] => utility [patent_app_number] => 14/920621 [patent_app_country] => US [patent_app_date] => 2015-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 22 [patent_no_of_words] => 5484 [patent_no_of_claims] => 26 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14920621 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11221610 [patent_doc_number] => 09449953 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-20 [patent_title] => 'Package-on-package assembly and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/877949 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 16 [patent_no_of_words] => 2452 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877949 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11227504 [patent_doc_number] => 09455230 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-27 [patent_title] => 'Semiconductor packages and methods of fabricating the same' [patent_app_type] => utility [patent_app_number] => 14/878717 [patent_app_country] => US [patent_app_date] => 2015-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 22 [patent_no_of_words] => 12087 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 69 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14878717 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11578696 [patent_doc_number] => 09633966 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-04-25 [patent_title] => 'Stacked semiconductor package and manufacturing method thereof' [patent_app_type] => utility [patent_app_number] => 14/877373 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5959 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877373 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11557711 [patent_doc_number] => 20170103957 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-04-13 [patent_title] => 'FAN-OUT WAFER-LEVEL PACKAGING USING METAL FOIL LAMINATION' [patent_app_type] => utility [patent_app_number] => 14/877205 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 4725 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14877205 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11373931 [patent_doc_number] => 09543226 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2017-01-10 [patent_title] => 'Heat sink for a semiconductor chip device' [patent_app_type] => utility [patent_app_number] => 14/876933 [patent_app_country] => US [patent_app_date] => 2015-10-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2419 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 103 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14876933 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10718447 [patent_doc_number] => 20160064594 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'LIGHT-EMITTING DIODE' [patent_app_type] => utility [patent_app_number] => 14/874467 [patent_app_country] => US [patent_app_date] => 2015-10-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 9719 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14874467 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10495310 [patent_doc_number] => 20150380332 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2015-12-31 [patent_title] => 'Substrate Design with Balanced Metal and Solder Resist Density' [patent_app_type] => utility [patent_app_number] => 14/845799 [patent_app_country] => US [patent_app_date] => 2015-09-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 4061 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14845799 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11207884 [patent_doc_number] => 09437515 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2016-09-06 [patent_title] => 'Heat spreading layer with high thermal conductivity' [patent_app_type] => utility [patent_app_number] => 14/838524 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 13 [patent_no_of_words] => 4513 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838524 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10718131 [patent_doc_number] => 20160064278 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'ELECTRIC CONNECTION ELEMENT MANUFACTURING METHOD' [patent_app_type] => utility [patent_app_number] => 14/838976 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2652 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838976 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11227677 [patent_doc_number] => 09455403 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-09-27 [patent_title] => 'Semiconductor structure and method for manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/838500 [patent_app_country] => US [patent_app_date] => 2015-08-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 3741 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 170 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14838500 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11585851 [patent_doc_number] => 09640503 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-05-02 [patent_title] => 'Package substrate, semiconductor package and method of manufacturing the same' [patent_app_type] => utility [patent_app_number] => 14/837245 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 18 [patent_no_of_words] => 3572 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837245 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11475570 [patent_doc_number] => 20170062354 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-03-02 [patent_title] => 'INTEGRATED CIRCUIT STRUCTURE WITH METAL CRACK STOP AND METHODS OF FORMING SAME' [patent_app_type] => utility [patent_app_number] => 14/837461 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 6736 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837461 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11321624 [patent_doc_number] => 09520372 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2016-12-13 [patent_title] => 'Wafer level package (WLP) and method for forming the same' [patent_app_type] => utility [patent_app_number] => 14/837712 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 28 [patent_no_of_words] => 5335 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837712 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11802370 [patent_doc_number] => 09543271 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2017-01-10 [patent_title] => 'Semiconductor device having a sealing layer covering a semiconductor memory unit and a memory controller' [patent_app_type] => utility [patent_app_number] => 14/837997 [patent_app_country] => US [patent_app_date] => 2015-08-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 25 [patent_no_of_words] => 10663 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14837997 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 10718133 [patent_doc_number] => 20160064280 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-03-03 [patent_title] => 'METHOD FOR FORMING THREE-DIMENSIONAL INTERCONNECTION, CIRCUIT ARRANGEMENT COMPRISING THREE-DIMENSIONAL INTERCONNECTION, AND METAL FILM-FORMING COMPOSITION FOR THREE-DIMENSIONAL INTERCONNECTION' [patent_app_type] => utility [patent_app_number] => 14/836236 [patent_app_country] => US [patent_app_date] => 2015-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 23 [patent_figures_cnt] => 23 [patent_no_of_words] => 31018 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14836236 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11959365 [patent_doc_number] => 20170263516 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2017-09-14 [patent_title] => 'Semiconductor Device, and Alternator and Power Converter Using the Semiconductor Device' [patent_app_type] => utility [patent_app_number] => 15/509882 [patent_app_country] => US [patent_app_date] => 2015-08-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 19947 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15509882 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 11041926 [patent_doc_number] => 20160238882 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2016-08-18 [patent_title] => 'ARRAY SUBSTRATE AND FABRICATING METHOD THEREOF, AND DISPLAY APPARATUS' [patent_app_type] => utility [patent_app_number] => 14/908671 [patent_app_country] => US [patent_app_date] => 2015-08-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 5324 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14908671 [rel_patent_id] =>[rel_patent_doc_number] =>)