Search

Anthony L. Luo

Examiner (ID: 15953)

Most Active Art Unit
2465
Art Unit(s)
2465
Total Applications
321
Issued Applications
243
Pending Applications
0
Abandoned Applications
82

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 16325065 [patent_doc_number] => 10785047 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-09-22 [patent_title] => Smart thermostat control system [patent_app_type] => utility [patent_app_number] => 16/204694 [patent_app_country] => US [patent_app_date] => 2018-11-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 21 [patent_no_of_words] => 8824 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16204694 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/204694
Smart thermostat control system Nov 28, 2018 Issued
Array ( [id] => 14076953 [patent_doc_number] => 20190087364 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-03-21 [patent_title] => INTEGRATED CIRCUIT MEMORY DEVICES WITH CUSTOMIZABLE STANDARD CELL LOGIC [patent_app_type] => utility [patent_app_number] => 16/193527 [patent_app_country] => US [patent_app_date] => 2018-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5888 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -7 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16193527 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/193527
Integrated circuit memory devices with customizable standard cell logic Nov 15, 2018 Issued
Array ( [id] => 18119670 [patent_doc_number] => 11551065 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2023-01-10 [patent_title] => Neural network architecture using control logic determining convolution operation sequence [patent_app_type] => utility [patent_app_number] => 16/182369 [patent_app_country] => US [patent_app_date] => 2018-11-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 17511 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16182369 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/182369
Neural network architecture using control logic determining convolution operation sequence Nov 5, 2018 Issued
Array ( [id] => 16201715 [patent_doc_number] => 10726890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-07-28 [patent_title] => Resistive memory apparatus and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/177460 [patent_app_country] => US [patent_app_date] => 2018-11-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 4514 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16177460 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/177460
Resistive memory apparatus and operating method thereof Oct 31, 2018 Issued
Array ( [id] => 15577769 [patent_doc_number] => 10579263 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-03-03 [patent_title] => Memory system [patent_app_type] => utility [patent_app_number] => 16/169178 [patent_app_country] => US [patent_app_date] => 2018-10-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 11388 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16169178 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/169178
Memory system Oct 23, 2018 Issued
Array ( [id] => 15249759 [patent_doc_number] => 10510406 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-17 [patent_title] => Soft-verify write assist circuit of resistive memory and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/168815 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 11 [patent_no_of_words] => 4754 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168815 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168815
Soft-verify write assist circuit of resistive memory and operating method thereof Oct 22, 2018 Issued
Array ( [id] => 16047671 [patent_doc_number] => 10685714 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-16 [patent_title] => Memory device for performing a selective erase operation and memory system having the same [patent_app_type] => utility [patent_app_number] => 16/168380 [patent_app_country] => US [patent_app_date] => 2018-10-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 15 [patent_no_of_words] => 8489 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16168380 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/168380
Memory device for performing a selective erase operation and memory system having the same Oct 22, 2018 Issued
Array ( [id] => 16339316 [patent_doc_number] => 10790285 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-29 [patent_title] => Multi-division 3D NAND memory device [patent_app_type] => utility [patent_app_number] => 16/166813 [patent_app_country] => US [patent_app_date] => 2018-10-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 7456 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16166813 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/166813
Multi-division 3D NAND memory device Oct 21, 2018 Issued
Array ( [id] => 14888691 [patent_doc_number] => 10424392 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-09-24 [patent_title] => Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods [patent_app_type] => utility [patent_app_number] => 16/165549 [patent_app_country] => US [patent_app_date] => 2018-10-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 9993 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 139 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16165549 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/165549
Read-assist circuits for memory bit cells employing a P-type field-effect transistor (PFET) read port(s), and related memory systems and methods Oct 18, 2018 Issued
Array ( [id] => 16234612 [patent_doc_number] => 10742181 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-08-11 [patent_title] => Buffer circuit to adjust signal voltage and memory device having the same [patent_app_type] => utility [patent_app_number] => 16/164187 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 8038 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16164187 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/164187
Buffer circuit to adjust signal voltage and memory device having the same Oct 17, 2018 Issued
Array ( [id] => 14315231 [patent_doc_number] => 20190147319 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-05-16 [patent_title] => DEVICE AND METHOD FOR PROCESSING CONVOLUTION OPERATION USING KERNEL [patent_app_type] => utility [patent_app_number] => 16/163772 [patent_app_country] => US [patent_app_date] => 2018-10-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8678 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 70 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16163772 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/163772
Device and method for processing convolution operation using kernel Oct 17, 2018 Issued
Array ( [id] => 15957033 [patent_doc_number] => 10666438 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Balanced coupling structure for physically unclonable function (PUF) application [patent_app_type] => utility [patent_app_number] => 16/160397 [patent_app_country] => US [patent_app_date] => 2018-10-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 13 [patent_figures_cnt] => 13 [patent_no_of_words] => 10390 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16160397 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/160397
Balanced coupling structure for physically unclonable function (PUF) application Oct 14, 2018 Issued
Array ( [id] => 15954799 [patent_doc_number] => 10665312 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-05-26 [patent_title] => Nonvolatile memory device configured to adjust a read parameter based on a degradation level [patent_app_type] => utility [patent_app_number] => 16/154111 [patent_app_country] => US [patent_app_date] => 2018-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 23 [patent_no_of_words] => 16350 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16154111 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/154111
Nonvolatile memory device configured to adjust a read parameter based on a degradation level Oct 7, 2018 Issued
Array ( [id] => 15642569 [patent_doc_number] => 10594302 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-03-17 [patent_title] => Voltage detection system [patent_app_type] => utility [patent_app_number] => 16/151305 [patent_app_country] => US [patent_app_date] => 2018-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 3755 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16151305 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/151305
Voltage detection system Oct 2, 2018 Issued
Array ( [id] => 15597135 [patent_doc_number] => 20200075102 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-03-05 [patent_title] => PROGRAMMING OF MEMORY CELLS IN THREE-DIMENSIONAL MEMORY DEVICES [patent_app_type] => utility [patent_app_number] => 16/149099 [patent_app_country] => US [patent_app_date] => 2018-10-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6686 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -15 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16149099 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/149099
Programming of memory cells in three-dimensional memory devices Sep 30, 2018 Issued
Array ( [id] => 15717177 [patent_doc_number] => 20200105356 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-04-02 [patent_title] => HOT CARRIER INJECTION FUSE MEMORY [patent_app_type] => utility [patent_app_number] => 16/147119 [patent_app_country] => US [patent_app_date] => 2018-09-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8335 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 186 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16147119 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/147119
Hot carrier injection fuse memory Sep 27, 2018 Issued
Array ( [id] => 14475097 [patent_doc_number] => 20190189194 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-06-20 [patent_title] => SEMICONDUCTOR MEMORY DEVICES, MEMORY SYSTEMS AND METHODS OF OPERATING A SEMICONDUCTOR MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 16/140053 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11248 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16140053 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/140053
Semiconductor memory devices, memory systems and refresh methods of the same Sep 23, 2018 Issued
Array ( [id] => 14676019 [patent_doc_number] => 20190237124 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND ELECTRONIC DEVICE INCLUDING THE SAME [patent_app_type] => utility [patent_app_number] => 16/139721 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7705 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 53 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139721 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/139721
Semiconductor memory device including a controller for controlling power and electronic device including the semiconductor memory device Sep 23, 2018 Issued
Array ( [id] => 13847425 [patent_doc_number] => 20190027197 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-24 [patent_title] => APPARATUSES AND METHODS FOR PROVIDING INTERNAL MEMORY COMMANDS AND CONTROL SIGNALS IN SEMICONDUCTOR MEMORIES [patent_app_type] => utility [patent_app_number] => 16/138517 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11791 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 41 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138517 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138517
Apparatuses and methods for providing internal memory commands and control signals in semiconductor memories Sep 20, 2018 Issued
Array ( [id] => 13875551 [patent_doc_number] => 20190034116 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => DATA TRANSFER BETWEEN SUBARRAYS IN MEMORY [patent_app_type] => utility [patent_app_number] => 16/138287 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13349 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138287 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/138287
Data transfer between subarrays in memory Sep 20, 2018 Issued
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