Search

Anthony M. Sol

Examiner (ID: 17667)

Most Active Art Unit
2465
Art Unit(s)
2619, 2465, 2419, 2616, 2662
Total Applications
247
Issued Applications
177
Pending Applications
12
Abandoned Applications
58

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 7535898 [patent_doc_number] => 08049532 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-01 [patent_title] => 'Level shifter circuit with a thin gate oxide transistor' [patent_app_type] => utility [patent_app_number] => 12/823596 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3854 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 124 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/049/08049532.pdf [firstpage_image] =>[orig_patent_app_number] => 12823596 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823596
Level shifter circuit with a thin gate oxide transistor Jun 24, 2010 Issued
Array ( [id] => 7667317 [patent_doc_number] => 20110316586 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-12-29 [patent_title] => 'LOW-VOLTAGE TO HIGH-VOLTAGE LEVEL TRANSLATION USING CAPACITIVE COUPLING' [patent_app_type] => utility [patent_app_number] => 12/823666 [patent_app_country] => US [patent_app_date] => 2010-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1736 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12823666 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/823666
Low-voltage to high-voltage level translation using capacitive coupling Jun 24, 2010 Issued
Array ( [id] => 7551327 [patent_doc_number] => 08063661 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-11-22 [patent_title] => 'Semiconductor device having circuit blocks with mutually the same circuit configuration' [patent_app_type] => utility [patent_app_number] => 12/820544 [patent_app_country] => US [patent_app_date] => 2010-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 25 [patent_figures_cnt] => 25 [patent_no_of_words] => 10942 [patent_no_of_claims] => 23 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 192 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/063/08063661.pdf [firstpage_image] =>[orig_patent_app_number] => 12820544 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/820544
Semiconductor device having circuit blocks with mutually the same circuit configuration Jun 21, 2010 Issued
Array ( [id] => 4597542 [patent_doc_number] => 07982497 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-07-19 [patent_title] => 'Multiplexer-based interconnection network' [patent_app_type] => utility [patent_app_number] => 12/819900 [patent_app_country] => US [patent_app_date] => 2010-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6150 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/982/07982497.pdf [firstpage_image] =>[orig_patent_app_number] => 12819900 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/819900
Multiplexer-based interconnection network Jun 20, 2010 Issued
Array ( [id] => 7724808 [patent_doc_number] => 08098081 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-17 [patent_title] => 'Optimization of interconnection networks' [patent_app_type] => utility [patent_app_number] => 12/819903 [patent_app_country] => US [patent_app_date] => 2010-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 8541 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/098/08098081.pdf [firstpage_image] =>[orig_patent_app_number] => 12819903 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/819903
Optimization of interconnection networks Jun 20, 2010 Issued
Array ( [id] => 7764090 [patent_doc_number] => 08115511 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-02-14 [patent_title] => 'Method for fabrication of a semiconductor device and structure' [patent_app_type] => utility [patent_app_number] => 12/797493 [patent_app_country] => US [patent_app_date] => 2010-06-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 178 [patent_figures_cnt] => 251 [patent_no_of_words] => 37491 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 67 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/115/08115511.pdf [firstpage_image] =>[orig_patent_app_number] => 12797493 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/797493
Method for fabrication of a semiconductor device and structure Jun 8, 2010 Issued
Array ( [id] => 8726300 [patent_doc_number] => 08405426 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2013-03-26 [patent_title] => 'Method and apparatus to serialize parallel data input values' [patent_app_type] => utility [patent_app_number] => 12/789566 [patent_app_country] => US [patent_app_date] => 2010-05-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 15950 [patent_no_of_claims] => 36 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 26 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12789566 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/789566
Method and apparatus to serialize parallel data input values May 27, 2010 Issued
Array ( [id] => 7541049 [patent_doc_number] => 08058895 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-11-15 [patent_title] => 'Single-resistor static programming circuits and methods' [patent_app_type] => utility [patent_app_number] => 12/799366 [patent_app_country] => US [patent_app_date] => 2010-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 1847 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 160 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/058/08058895.pdf [firstpage_image] =>[orig_patent_app_number] => 12799366 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/799366
Single-resistor static programming circuits and methods Apr 22, 2010 Issued
Array ( [id] => 7731238 [patent_doc_number] => 08102188 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2012-01-24 [patent_title] => 'Method of and system for implementing a circuit in a device having programmable logic' [patent_app_type] => utility [patent_app_number] => 12/757770 [patent_app_country] => US [patent_app_date] => 2010-04-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 10 [patent_no_of_words] => 7234 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 104 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/102/08102188.pdf [firstpage_image] =>[orig_patent_app_number] => 12757770 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/757770
Method of and system for implementing a circuit in a device having programmable logic Apr 8, 2010 Issued
Array ( [id] => 4518796 [patent_doc_number] => 07911231 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2011-03-22 [patent_title] => 'Semiconductor integrated circuit device' [patent_app_type] => utility [patent_app_number] => 12/728388 [patent_app_country] => US [patent_app_date] => 2010-03-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 2761 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 261 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/911/07911231.pdf [firstpage_image] =>[orig_patent_app_number] => 12728388 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/728388
Semiconductor integrated circuit device Mar 21, 2010 Issued
Array ( [id] => 6324417 [patent_doc_number] => 20100244901 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-09-30 [patent_title] => 'CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS' [patent_app_type] => utility [patent_app_number] => 12/726595 [patent_app_country] => US [patent_app_date] => 2010-03-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 7931 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0244/20100244901.pdf [firstpage_image] =>[orig_patent_app_number] => 12726595 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/726595
CLOCK SWITCHING CIRCUIT, INTEGRATED CIRCUIT DEVICE AND ELECTRONIC APPARATUS Mar 17, 2010 Abandoned
Array ( [id] => 4614729 [patent_doc_number] => 07990173 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-08-02 [patent_title] => 'Single event upset mitigation' [patent_app_type] => utility [patent_app_number] => 12/725324 [patent_app_country] => US [patent_app_date] => 2010-03-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 5002 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 183 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/990/07990173.pdf [firstpage_image] =>[orig_patent_app_number] => 12725324 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/725324
Single event upset mitigation Mar 15, 2010 Issued
Array ( [id] => 6200196 [patent_doc_number] => 20110062982 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2011-03-17 [patent_title] => 'SEMICONDUCTOR INTEGRATED CIRCUIT' [patent_app_type] => utility [patent_app_number] => 12/717442 [patent_app_country] => US [patent_app_date] => 2010-03-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 4757 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0062/20110062982.pdf [firstpage_image] =>[orig_patent_app_number] => 12717442 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/717442
Semiconductor integrated circuit for reducing crosstalk Mar 3, 2010 Issued
Array ( [id] => 6282331 [patent_doc_number] => 20100156459 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-24 [patent_title] => 'PROGRAMMABLE DELAY LINE COMPENSATED FOR PROCESS, VOLTAGE, AND TEMPERATURE' [patent_app_type] => utility [patent_app_number] => 12/716469 [patent_app_country] => US [patent_app_date] => 2010-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 14 [patent_no_of_words] => 8087 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0156/20100156459.pdf [firstpage_image] =>[orig_patent_app_number] => 12716469 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/716469
Programmable delay line compensated for process, voltage, and temperature Mar 2, 2010 Issued
Array ( [id] => 8556083 [patent_doc_number] => 08330558 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2012-12-11 [patent_title] => 'Filter and antenna duplexer' [patent_app_type] => utility [patent_app_number] => 12/700876 [patent_app_country] => US [patent_app_date] => 2010-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 40 [patent_figures_cnt] => 88 [patent_no_of_words] => 14476 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 166 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 12700876 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/700876
Filter and antenna duplexer Feb 4, 2010 Issued
Array ( [id] => 7516078 [patent_doc_number] => 08040152 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2011-10-18 [patent_title] => 'Separate configuration of I/O cells and logic core in a programmable logic device' [patent_app_type] => utility [patent_app_number] => 12/698283 [patent_app_country] => US [patent_app_date] => 2010-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3704 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/08/040/08040152.pdf [firstpage_image] =>[orig_patent_app_number] => 12698283 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/698283
Separate configuration of I/O cells and logic core in a programmable logic device Feb 1, 2010 Issued
Array ( [id] => 6241484 [patent_doc_number] => 20100134138 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-06-03 [patent_title] => 'Programmable logic device structure using third dimensional memory' [patent_app_type] => utility [patent_app_number] => 12/657684 [patent_app_country] => US [patent_app_date] => 2010-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5026 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0134/20100134138.pdf [firstpage_image] =>[orig_patent_app_number] => 12657684 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/657684
Programmable logic device structure using third dimensional memory Jan 24, 2010 Issued
Array ( [id] => 5501 [patent_doc_number] => 07816942 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2010-10-19 [patent_title] => 'USB 2.0 HS voltage-mode transmitter with tuned termination resistance' [patent_app_type] => utility [patent_app_number] => 12/687067 [patent_app_country] => US [patent_app_date] => 2010-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3755 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/07/816/07816942.pdf [firstpage_image] =>[orig_patent_app_number] => 12687067 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/687067
USB 2.0 HS voltage-mode transmitter with tuned termination resistance Jan 12, 2010 Issued
Array ( [id] => 6579737 [patent_doc_number] => 20100097099 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-22 [patent_title] => 'FPGA Having a Direct Routing Structure' [patent_app_type] => utility [patent_app_number] => 12/645236 [patent_app_country] => US [patent_app_date] => 2009-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 3399 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0097/20100097099.pdf [firstpage_image] =>[orig_patent_app_number] => 12645236 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/645236
FPGA having a direct routing structure Dec 21, 2009 Issued
Array ( [id] => 6344048 [patent_doc_number] => 20100085079 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2010-04-08 [patent_title] => 'Low Latency, Power-Down Safe Level Shifter' [patent_app_type] => utility [patent_app_number] => 12/634791 [patent_app_country] => US [patent_app_date] => 2009-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6644 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 0 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] => publications/A1/0085/20100085079.pdf [firstpage_image] =>[orig_patent_app_number] => 12634791 [rel_patent_id] =>[rel_patent_doc_number] =>)
12/634791
Low latency, power-down safe level shifter Dec 9, 2009 Issued
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