
Anthony T. Whittington
Examiner (ID: 508)
| Most Active Art Unit | 2127 |
| Art Unit(s) | 2133, 2126, 2127, 2121 |
| Total Applications | 359 |
| Issued Applications | 290 |
| Pending Applications | 0 |
| Abandoned Applications | 72 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 1292357
[patent_doc_number] => 06643816
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-04
[patent_title] => 'Transmitting apparatus and error handling method in transmitting apparatus'
[patent_app_type] => B1
[patent_app_number] => 09/662648
[patent_app_country] => US
[patent_app_date] => 2000-09-14
[patent_effective_date] => 0000-00-00
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[patent_no_of_words] => 4727
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[pdf_file] => patents/06/643/06643816.pdf
[firstpage_image] =>[orig_patent_app_number] => 09662648
[rel_patent_id] =>[rel_patent_doc_number] =>) 09/662648 | Transmitting apparatus and error handling method in transmitting apparatus | Sep 13, 2000 | Issued |
Array
(
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[patent_doc_number] => 06651209
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-11-18
[patent_title] => 'Parallel turbo coder implementation'
[patent_app_type] => B1
[patent_app_number] => 09/660290
[patent_app_country] => US
[patent_app_date] => 2000-09-12
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Array
(
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[patent_doc_number] => 06591385
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-07-08
[patent_title] => 'Method and apparatus for inserting programmable latency between address and data information in a memory tester'
[patent_app_type] => B1
[patent_app_number] => 09/659539
[patent_app_country] => US
[patent_app_date] => 2000-09-11
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[pdf_file] => patents/06/591/06591385.pdf
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/659539 | Method and apparatus for inserting programmable latency between address and data information in a memory tester | Sep 10, 2000 | Issued |
Array
(
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[patent_doc_number] => 06629287
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2003-09-30
[patent_title] => 'Channel decoder and method of channel decoding'
[patent_app_type] => B1
[patent_app_number] => 09/659093
[patent_app_country] => US
[patent_app_date] => 2000-09-11
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/659093 | Channel decoder and method of channel decoding | Sep 10, 2000 | Issued |
Array
(
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[patent_doc_number] => 06594793
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[patent_kind] => B1
[patent_issue_date] => 2003-07-15
[patent_title] => 'Methods and systems for multiplexing and decoding variable length messages in digital communications systems'
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[patent_app_number] => 09/659021
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[patent_app_date] => 2000-09-08
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Array
(
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[patent_doc_number] => 06609224
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[patent_title] => 'Replacement of transport-layer checksum in checksum-based header compression'
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Array
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[patent_title] => 'On-the-fly algebraic error correction system and method for reducing error location search'
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[patent_app_number] => 09/562575
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/562575 | On-the-fly algebraic error correction system and method for reducing error location search | Apr 30, 2000 | Issued |
Array
(
[id] => 1260662
[patent_doc_number] => 06668352
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[patent_issue_date] => 2003-12-23
[patent_title] => 'Distortion compensating device and method in a multi-code mobile communication system'
[patent_app_type] => B1
[patent_app_number] => 09/560733
[patent_app_country] => US
[patent_app_date] => 2000-04-28
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560733 | Distortion compensating device and method in a multi-code mobile communication system | Apr 27, 2000 | Issued |
Array
(
[id] => 1339907
[patent_doc_number] => 06601198
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[patent_issue_date] => 2003-07-29
[patent_title] => 'Semiconductor integrated circuit'
[patent_app_type] => B1
[patent_app_number] => 09/560885
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560885 | Semiconductor integrated circuit | Apr 27, 2000 | Issued |
Array
(
[id] => 1348649
[patent_doc_number] => 06598189
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[patent_issue_date] => 2003-07-22
[patent_title] => 'Method and apparatus for determining the rate and quality of received data in a variable rate digital communication system'
[patent_app_type] => B1
[patent_app_number] => 09/560648
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/560648 | Method and apparatus for determining the rate and quality of received data in a variable rate digital communication system | Apr 27, 2000 | Issued |
Array
(
[id] => 1324339
[patent_doc_number] => 06611936
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[patent_kind] => B2
[patent_issue_date] => 2003-08-26
[patent_title] => 'Programmable delay elements for source synchronous link function design verification through simulation'
[patent_app_type] => B2
[patent_app_number] => 09/560191
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Array
(
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[patent_issue_date] => 2003-09-30
[patent_title] => 'Method and apparatus for a scannable hybrid flip flop'
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Array
(
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[patent_title] => 'Method and device for collecting output logic values from a logic unit in an electronic circuit'
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Array
(
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[patent_title] => 'Comparable circuits for parallel testing DRAM device'
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Array
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Array
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Array
(
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Array
(
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Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/452042 | System and method for pruning a bridging diagnostic list | Nov 29, 1999 | Issued |
Array
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[rel_patent_id] =>[rel_patent_doc_number] =>) 09/432969 | Initial stage of a multi-stage algorithmic pattern generator for testing IC chips | Nov 2, 1999 | Issued |