Search

Anthony T. Whittington

Examiner (ID: 508)

Most Active Art Unit
2127
Art Unit(s)
2133, 2126, 2127, 2121
Total Applications
359
Issued Applications
290
Pending Applications
0
Abandoned Applications
72

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 1292357 [patent_doc_number] => 06643816 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-04 [patent_title] => 'Transmitting apparatus and error handling method in transmitting apparatus' [patent_app_type] => B1 [patent_app_number] => 09/662648 [patent_app_country] => US [patent_app_date] => 2000-09-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 4727 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 138 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/643/06643816.pdf [firstpage_image] =>[orig_patent_app_number] => 09662648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/662648
Transmitting apparatus and error handling method in transmitting apparatus Sep 13, 2000 Issued
Array ( [id] => 1284977 [patent_doc_number] => 06651209 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-11-18 [patent_title] => 'Parallel turbo coder implementation' [patent_app_type] => B1 [patent_app_number] => 09/660290 [patent_app_country] => US [patent_app_date] => 2000-09-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 8009 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/651/06651209.pdf [firstpage_image] =>[orig_patent_app_number] => 09660290 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/660290
Parallel turbo coder implementation Sep 11, 2000 Issued
Array ( [id] => 1357626 [patent_doc_number] => 06591385 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Method and apparatus for inserting programmable latency between address and data information in a memory tester' [patent_app_type] => B1 [patent_app_number] => 09/659539 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 10690 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 116 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591385.pdf [firstpage_image] =>[orig_patent_app_number] => 09659539 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659539
Method and apparatus for inserting programmable latency between address and data information in a memory tester Sep 10, 2000 Issued
Array ( [id] => 1309371 [patent_doc_number] => 06629287 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Channel decoder and method of channel decoding' [patent_app_type] => B1 [patent_app_number] => 09/659093 [patent_app_country] => US [patent_app_date] => 2000-09-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 2432 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 187 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629287.pdf [firstpage_image] =>[orig_patent_app_number] => 09659093 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659093
Channel decoder and method of channel decoding Sep 10, 2000 Issued
Array ( [id] => 1354006 [patent_doc_number] => 06594793 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-15 [patent_title] => 'Methods and systems for multiplexing and decoding variable length messages in digital communications systems' [patent_app_type] => B1 [patent_app_number] => 09/659021 [patent_app_country] => US [patent_app_date] => 2000-09-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 10 [patent_no_of_words] => 8148 [patent_no_of_claims] => 42 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 68 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/594/06594793.pdf [firstpage_image] =>[orig_patent_app_number] => 09659021 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/659021
Methods and systems for multiplexing and decoding variable length messages in digital communications systems Sep 7, 2000 Issued
Array ( [id] => 1327142 [patent_doc_number] => 06609224 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-08-19 [patent_title] => 'Replacement of transport-layer checksum in checksum-based header compression' [patent_app_type] => B1 [patent_app_number] => 09/657350 [patent_app_country] => US [patent_app_date] => 2000-09-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 2897 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/609/06609224.pdf [firstpage_image] =>[orig_patent_app_number] => 09657350 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/657350
Replacement of transport-layer checksum in checksum-based header compression Sep 6, 2000 Issued
Array ( [id] => 1258656 [patent_doc_number] => 06671850 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-30 [patent_title] => 'On-the-fly algebraic error correction system and method for reducing error location search' [patent_app_type] => B1 [patent_app_number] => 09/562575 [patent_app_country] => US [patent_app_date] => 2000-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 5586 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 130 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/671/06671850.pdf [firstpage_image] =>[orig_patent_app_number] => 09562575 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/562575
On-the-fly algebraic error correction system and method for reducing error location search Apr 30, 2000 Issued
Array ( [id] => 1260662 [patent_doc_number] => 06668352 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-23 [patent_title] => 'Distortion compensating device and method in a multi-code mobile communication system' [patent_app_type] => B1 [patent_app_number] => 09/560733 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 3255 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/668/06668352.pdf [firstpage_image] =>[orig_patent_app_number] => 09560733 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560733
Distortion compensating device and method in a multi-code mobile communication system Apr 27, 2000 Issued
Array ( [id] => 1339907 [patent_doc_number] => 06601198 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-29 [patent_title] => 'Semiconductor integrated circuit' [patent_app_type] => B1 [patent_app_number] => 09/560885 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 4692 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 128 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/601/06601198.pdf [firstpage_image] =>[orig_patent_app_number] => 09560885 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560885
Semiconductor integrated circuit Apr 27, 2000 Issued
Array ( [id] => 1348649 [patent_doc_number] => 06598189 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-22 [patent_title] => 'Method and apparatus for determining the rate and quality of received data in a variable rate digital communication system' [patent_app_type] => B1 [patent_app_number] => 09/560648 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 4333 [patent_no_of_claims] => 39 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 253 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/598/06598189.pdf [firstpage_image] =>[orig_patent_app_number] => 09560648 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560648
Method and apparatus for determining the rate and quality of received data in a variable rate digital communication system Apr 27, 2000 Issued
Array ( [id] => 1324339 [patent_doc_number] => 06611936 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2003-08-26 [patent_title] => 'Programmable delay elements for source synchronous link function design verification through simulation' [patent_app_type] => B2 [patent_app_number] => 09/560191 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 2613 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/611/06611936.pdf [firstpage_image] =>[orig_patent_app_number] => 09560191 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/560191
Programmable delay elements for source synchronous link function design verification through simulation Apr 27, 2000 Issued
Array ( [id] => 1309278 [patent_doc_number] => 06629276 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-30 [patent_title] => 'Method and apparatus for a scannable hybrid flip flop' [patent_app_type] => B1 [patent_app_number] => 09/559660 [patent_app_country] => US [patent_app_date] => 2000-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 6113 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 98 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/629/06629276.pdf [firstpage_image] =>[orig_patent_app_number] => 09559660 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/559660
Method and apparatus for a scannable hybrid flip flop Apr 27, 2000 Issued
Array ( [id] => 1311792 [patent_doc_number] => 06625767 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Method and device for collecting output logic values from a logic unit in an electronic circuit' [patent_app_type] => B1 [patent_app_number] => 09/558935 [patent_app_country] => US [patent_app_date] => 2000-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 12 [patent_no_of_words] => 4175 [patent_no_of_claims] => 43 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625767.pdf [firstpage_image] =>[orig_patent_app_number] => 09558935 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/558935
Method and device for collecting output logic values from a logic unit in an electronic circuit Apr 25, 2000 Issued
Array ( [id] => 1357616 [patent_doc_number] => 06591384 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-07-08 [patent_title] => 'Comparable circuits for parallel testing DRAM device' [patent_app_type] => B1 [patent_app_number] => 09/557443 [patent_app_country] => US [patent_app_date] => 2000-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 2221 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 158 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/591/06591384.pdf [firstpage_image] =>[orig_patent_app_number] => 09557443 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/557443
Comparable circuits for parallel testing DRAM device Apr 24, 2000 Issued
Array ( [id] => 1311827 [patent_doc_number] => 06625772 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-23 [patent_title] => 'Circuit arrangement and method for minimizing bit errors' [patent_app_type] => B1 [patent_app_number] => 09/486943 [patent_app_country] => US [patent_app_date] => 2000-03-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 2445 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 78 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/625/06625772.pdf [firstpage_image] =>[orig_patent_app_number] => 09486943 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/486943
Circuit arrangement and method for minimizing bit errors Mar 1, 2000 Issued
Array ( [id] => 1297394 [patent_doc_number] => 06634003 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-10-14 [patent_title] => 'Decoding circuit for memories with redundancy' [patent_app_type] => B1 [patent_app_number] => 09/501807 [patent_app_country] => US [patent_app_date] => 2000-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 5047 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 97 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/634/06634003.pdf [firstpage_image] =>[orig_patent_app_number] => 09501807 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/501807
Decoding circuit for memories with redundancy Feb 9, 2000 Issued
Array ( [id] => 7633000 [patent_doc_number] => 06658620 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-12-02 [patent_title] => 'Burst and packet wireless transmission using product codes with iterative decoding' [patent_app_type] => B1 [patent_app_number] => 09/481082 [patent_app_country] => US [patent_app_date] => 2000-01-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2378 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 14 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/658/06658620.pdf [firstpage_image] =>[orig_patent_app_number] => 09481082 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/481082
Burst and packet wireless transmission using product codes with iterative decoding Jan 10, 2000 Issued
Array ( [id] => 1410438 [patent_doc_number] => 06557141 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-04-29 [patent_title] => 'Magnetic media certification' [patent_app_type] => B1 [patent_app_number] => 09/452519 [patent_app_country] => US [patent_app_date] => 1999-12-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 3753 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/557/06557141.pdf [firstpage_image] =>[orig_patent_app_number] => 09452519 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452519
Magnetic media certification Nov 30, 1999 Issued
Array ( [id] => 1319393 [patent_doc_number] => 06618830 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-09-09 [patent_title] => 'System and method for pruning a bridging diagnostic list' [patent_app_type] => B1 [patent_app_number] => 09/452042 [patent_app_country] => US [patent_app_date] => 1999-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5528 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 119 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/618/06618830.pdf [firstpage_image] =>[orig_patent_app_number] => 09452042 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/452042
System and method for pruning a bridging diagnostic list Nov 29, 1999 Issued
Array ( [id] => 1386689 [patent_doc_number] => 06571365 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2003-05-27 [patent_title] => 'Initial stage of a multi-stage algorithmic pattern generator for testing IC chips' [patent_app_type] => B1 [patent_app_number] => 09/432969 [patent_app_country] => US [patent_app_date] => 1999-11-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 29 [patent_figures_cnt] => 36 [patent_no_of_words] => 27811 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 217 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/06/571/06571365.pdf [firstpage_image] =>[orig_patent_app_number] => 09432969 [rel_patent_id] =>[rel_patent_doc_number] =>)
09/432969
Initial stage of a multi-stage algorithmic pattern generator for testing IC chips Nov 2, 1999 Issued
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