Search

Aracelis Ruiz

Examiner (ID: 8312, Phone: (571)270-1038 , Office: P/2139 )

Most Active Art Unit
2139
Art Unit(s)
2189, 2139
Total Applications
1042
Issued Applications
879
Pending Applications
67
Abandoned Applications
116

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 20587224 [patent_doc_number] => 20260072819 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-12 [patent_title] => MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 19/098342 [patent_app_country] => US [patent_app_date] => 2025-04-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3652 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 109 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19098342 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/098342
MEMORY DEVICE Apr 1, 2025 Pending
Array ( [id] => 20310635 [patent_doc_number] => 20250328264 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => ADJUSTED ACCESS OPERATIONS FOR REPLAY PROTECTED MEMORY BLOCKS [patent_app_type] => utility [patent_app_number] => 19/097499 [patent_app_country] => US [patent_app_date] => 2025-04-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8589 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19097499 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/097499
ADJUSTED ACCESS OPERATIONS FOR REPLAY PROTECTED MEMORY BLOCKS Mar 31, 2025 Pending
Array ( [id] => 20310618 [patent_doc_number] => 20250328247 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-10-23 [patent_title] => FULL DUPLEX MEMORY SYSTEM [patent_app_type] => utility [patent_app_number] => 19/081580 [patent_app_country] => US [patent_app_date] => 2025-03-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7169 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19081580 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/081580
FULL DUPLEX MEMORY SYSTEM Mar 16, 2025 Pending
Array ( [id] => 20601618 [patent_doc_number] => 20260079627 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2026-03-19 [patent_title] => MEMORY SYSTEM WITH TEMPERATURE-BASED READ VOLTAGE ADJUSTMENT [patent_app_type] => utility [patent_app_number] => 19/066373 [patent_app_country] => US [patent_app_date] => 2025-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 8916 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 90 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19066373 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/066373
MEMORY SYSTEM WITH TEMPERATURE-BASED READ VOLTAGE ADJUSTMENT Feb 27, 2025 Pending
Array ( [id] => 20208473 [patent_doc_number] => 20250278193 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-04 [patent_title] => MANAGING I/O OPERATIONS ASSOCIATED WITH A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 19/045769 [patent_app_country] => US [patent_app_date] => 2025-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3501 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 133 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19045769 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/045769
MANAGING I/O OPERATIONS ASSOCIATED WITH A COMPUTE EXPRESS LINK (CXL) MEMORY DEVICE Feb 4, 2025 Pending
Array ( [id] => 20027182 [patent_doc_number] => 20250165404 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => System Control Using Sparse Data [patent_app_type] => utility [patent_app_number] => 19/029681 [patent_app_country] => US [patent_app_date] => 2025-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9102 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19029681 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/029681
System Control Using Sparse Data Jan 16, 2025 Pending
Array ( [id] => 20101750 [patent_doc_number] => 20250231686 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-17 [patent_title] => MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT [patent_app_type] => utility [patent_app_number] => 19/018436 [patent_app_country] => US [patent_app_date] => 2025-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 0 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19018436 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/018436
MEMORY SYSTEM WITH THREADED TRANSACTION SUPPORT Jan 12, 2025 Pending
Array ( [id] => 20087133 [patent_doc_number] => 20250217069 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-03 [patent_title] => STREAMING MATRIX TRANSPOSER WITH DIAGONAL STORAGE [patent_app_type] => utility [patent_app_number] => 19/001251 [patent_app_country] => US [patent_app_date] => 2024-12-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7478 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19001251 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/001251
STREAMING MATRIX TRANSPOSER WITH DIAGONAL STORAGE Dec 23, 2024 Pending
Array ( [id] => 19985527 [patent_doc_number] => 20250123749 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => DETECTION OF MEMORY ACCESSES [patent_app_type] => utility [patent_app_number] => 19/000448 [patent_app_country] => US [patent_app_date] => 2024-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3449 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 82 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 19000448 [rel_patent_id] =>[rel_patent_doc_number] =>)
19/000448
DETECTION OF MEMORY ACCESSES Dec 22, 2024 Pending
Array ( [id] => 19985546 [patent_doc_number] => 20250123768 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-04-17 [patent_title] => Optimizing Storage System Power Consumption Using Dynamic Plane Selection [patent_app_type] => utility [patent_app_number] => 18/987445 [patent_app_country] => US [patent_app_date] => 2024-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 35863 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 91 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18987445 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/987445
Optimizing Storage System Power Consumption Using Dynamic Plane Selection Dec 18, 2024 Pending
Array ( [id] => 20094935 [patent_doc_number] => 20250224871 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-07-10 [patent_title] => ENHANCEMENTS FOR MULTIPLE DATA PLANE READ COMMANDS [patent_app_type] => utility [patent_app_number] => 18/985636 [patent_app_country] => US [patent_app_date] => 2024-12-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 10605 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -30 [patent_words_short_claim] => 105 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18985636 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/985636
ENHANCEMENTS FOR MULTIPLE DATA PLANE READ COMMANDS Dec 17, 2024 Pending
Array ( [id] => 20234405 [patent_doc_number] => 20250291724 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-18 [patent_title] => COMMUNICATION SYSTEM [patent_app_type] => utility [patent_app_number] => 18/982791 [patent_app_country] => US [patent_app_date] => 2024-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 23027 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 289 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18982791 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/982791
COMMUNICATION SYSTEM Dec 15, 2024 Pending
Array ( [id] => 20061483 [patent_doc_number] => 20250199705 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-06-19 [patent_title] => MEMORY ARCHITECTURE FOR BLOCK MIGRATION IN ZNS [patent_app_type] => utility [patent_app_number] => 18/980680 [patent_app_country] => US [patent_app_date] => 2024-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5072 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 154 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18980680 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/980680
MEMORY ARCHITECTURE FOR BLOCK MIGRATION IN ZNS Dec 12, 2024 Pending
Array ( [id] => 20249642 [patent_doc_number] => 20250298511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-09-25 [patent_title] => MEMORY STATUS BASED TRAFFIC ROUTING ON HETEROGENEOUS MEMORY SUBSYSTEM [patent_app_type] => utility [patent_app_number] => 18/956020 [patent_app_country] => US [patent_app_date] => 2024-11-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5249 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -22 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18956020 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/956020
MEMORY STATUS BASED TRAFFIC ROUTING ON HETEROGENEOUS MEMORY SUBSYSTEM Nov 21, 2024 Pending
Array ( [id] => 19818869 [patent_doc_number] => 20250077076 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-03-06 [patent_title] => NON-DETERMINISTIC MEMORY PROTOCOL [patent_app_type] => utility [patent_app_number] => 18/954809 [patent_app_country] => US [patent_app_date] => 2024-11-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7213 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18954809 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/954809
NON-DETERMINISTIC MEMORY PROTOCOL Nov 20, 2024 Pending
Array ( [id] => 20026967 [patent_doc_number] => 20250165189 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-05-22 [patent_title] => BIT STRING ARBITER COMPONENTS [patent_app_type] => utility [patent_app_number] => 18/948878 [patent_app_country] => US [patent_app_date] => 2024-11-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 3858 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 84 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18948878 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/948878
BIT STRING ARBITER COMPONENTS Nov 14, 2024 Pending
Array ( [id] => 19772085 [patent_doc_number] => 20250053511 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-02-13 [patent_title] => SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS MEMORY AREAS [patent_app_type] => utility [patent_app_number] => 18/928244 [patent_app_country] => US [patent_app_date] => 2024-10-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 13242 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18928244 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/928244
SYSTEM AND METHOD FOR SHARING A CACHE LINE BETWEEN NON-CONTIGUOUS MEMORY AREAS Oct 27, 2024 Pending
Array ( [id] => 19725800 [patent_doc_number] => 20250028551 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-23 [patent_title] => GLOBAL COHERENCE OPERATIONS [patent_app_type] => utility [patent_app_number] => 18/908970 [patent_app_country] => US [patent_app_date] => 2024-10-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 17707 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18908970 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/908970
GLOBAL COHERENCE OPERATIONS Oct 7, 2024 Pending
Array ( [id] => 19694739 [patent_doc_number] => 20250013284 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS [patent_app_type] => utility [patent_app_number] => 18/894180 [patent_app_country] => US [patent_app_date] => 2024-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4640 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18894180 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/894180
STATIC POWER REDUCTION IN CACHES USING DETERMINISTIC NAPS Sep 23, 2024 Pending
Array ( [id] => 19695017 [patent_doc_number] => 20250013562 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2025-01-09 [patent_title] => SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE [patent_app_type] => utility [patent_app_number] => 18/887886 [patent_app_country] => US [patent_app_date] => 2024-09-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11755 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -19 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18887886 [rel_patent_id] =>[rel_patent_doc_number] =>)
18/887886
SYNCHRONIZED REQUEST HANDLING AT A MEMORY DEVICE Sep 16, 2024 Pending
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