Search

Aradhana Sasan

Examiner (ID: 18925, Phone: (571)272-9022 , Office: P/1615 )

Most Active Art Unit
1615
Art Unit(s)
1615
Total Applications
1310
Issued Applications
754
Pending Applications
115
Abandoned Applications
467

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 3871058 [patent_doc_number] => 05706466 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Von Neumann system with harvard processor and instruction buffer' [patent_app_type] => 1 [patent_app_number] => 8/372531 [patent_app_country] => US [patent_app_date] => 1995-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 6393 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706466.pdf [firstpage_image] =>[orig_patent_app_number] => 372531 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/372531
Von Neumann system with harvard processor and instruction buffer Jan 12, 1995 Issued
Array ( [id] => 3632127 [patent_doc_number] => 05642479 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-24 [patent_title] => 'Trace analysis of data processing' [patent_app_type] => 1 [patent_app_number] => 8/368837 [patent_app_country] => US [patent_app_date] => 1995-01-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 5408 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 100 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/642/05642479.pdf [firstpage_image] =>[orig_patent_app_number] => 368837 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368837
Trace analysis of data processing Jan 4, 1995 Issued
Array ( [id] => 3635961 [patent_doc_number] => 05594882 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-14 [patent_title] => 'PCI split transactions utilizing dual address cycle' [patent_app_type] => 1 [patent_app_number] => 8/368332 [patent_app_country] => US [patent_app_date] => 1995-01-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 5 [patent_no_of_words] => 6272 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/594/05594882.pdf [firstpage_image] =>[orig_patent_app_number] => 368332 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368332
PCI split transactions utilizing dual address cycle Jan 3, 1995 Issued
Array ( [id] => 3672842 [patent_doc_number] => 05592657 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Console simulator, multi-console management system, and console management distribution system' [patent_app_type] => 1 [patent_app_number] => 8/367950 [patent_app_country] => US [patent_app_date] => 1995-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 14744 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 143 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592657.pdf [firstpage_image] =>[orig_patent_app_number] => 367950 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/367950
Console simulator, multi-console management system, and console management distribution system Jan 2, 1995 Issued
Array ( [id] => 3735923 [patent_doc_number] => 05673410 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-09-30 [patent_title] => 'System for aligning varying width instructions in a computer' [patent_app_type] => 1 [patent_app_number] => 8/368225 [patent_app_country] => US [patent_app_date] => 1995-01-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 22 [patent_no_of_words] => 4879 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/673/05673410.pdf [firstpage_image] =>[orig_patent_app_number] => 368225 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/368225
System for aligning varying width instructions in a computer Jan 2, 1995 Issued
Array ( [id] => 3672704 [patent_doc_number] => 05649119 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-07-15 [patent_title] => 'Data queuing apparatus' [patent_app_type] => 1 [patent_app_number] => 8/365637 [patent_app_country] => US [patent_app_date] => 1994-12-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 30 [patent_figures_cnt] => 43 [patent_no_of_words] => 13205 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 56 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/649/05649119.pdf [firstpage_image] =>[orig_patent_app_number] => 365637 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/365637
Data queuing apparatus Dec 27, 1994 Issued
Array ( [id] => 3636447 [patent_doc_number] => 05602998 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-11 [patent_title] => 'Dequeue instruction in a system architecture for improved message passing and process synchronization' [patent_app_type] => 1 [patent_app_number] => 8/362638 [patent_app_country] => US [patent_app_date] => 1994-12-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 5946 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/602/05602998.pdf [firstpage_image] =>[orig_patent_app_number] => 362638 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/362638
Dequeue instruction in a system architecture for improved message passing and process synchronization Dec 21, 1994 Issued
Array ( [id] => 3503191 [patent_doc_number] => 05561775 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-10-01 [patent_title] => 'Parallel processing apparatus and method capable of processing plural instructions in parallel or successively' [patent_app_type] => 1 [patent_app_number] => 8/360081 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 34 [patent_no_of_words] => 10652 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/561/05561775.pdf [firstpage_image] =>[orig_patent_app_number] => 360081 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360081
Parallel processing apparatus and method capable of processing plural instructions in parallel or successively Dec 19, 1994 Issued
Array ( [id] => 4022621 [patent_doc_number] => 05987613 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1999-11-16 [patent_title] => 'Portable computer with time-sensitive tri-modal power management switch' [patent_app_type] => 1 [patent_app_number] => 8/360194 [patent_app_country] => US [patent_app_date] => 1994-12-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 27 [patent_figures_cnt] => 27 [patent_no_of_words] => 11201 [patent_no_of_claims] => 38 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 136 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/987/05987613.pdf [firstpage_image] =>[orig_patent_app_number] => 360194 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/360194
Portable computer with time-sensitive tri-modal power management switch Dec 19, 1994 Issued
Array ( [id] => 3744039 [patent_doc_number] => 05636352 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-06-03 [patent_title] => 'Method and apparatus for utilizing condensed instructions' [patent_app_type] => 1 [patent_app_number] => 8/357835 [patent_app_country] => US [patent_app_date] => 1994-12-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 1945 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 54 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/636/05636352.pdf [firstpage_image] =>[orig_patent_app_number] => 357835 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/357835
Method and apparatus for utilizing condensed instructions Dec 15, 1994 Issued
Array ( [id] => 3611844 [patent_doc_number] => 05559955 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-09-24 [patent_title] => 'Method and apparatus for monitoring the status of non-pollable device in a computer network' [patent_app_type] => 1 [patent_app_number] => 8/355430 [patent_app_country] => US [patent_app_date] => 1994-12-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 16 [patent_no_of_words] => 11635 [patent_no_of_claims] => 29 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 222 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/559/05559955.pdf [firstpage_image] =>[orig_patent_app_number] => 355430 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/355430
Method and apparatus for monitoring the status of non-pollable device in a computer network Dec 12, 1994 Issued
Array ( [id] => 3562387 [patent_doc_number] => 05548744 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-20 [patent_title] => 'Memory circuit and method for setting an operation mode' [patent_app_type] => 1 [patent_app_number] => 8/354934 [patent_app_country] => US [patent_app_date] => 1994-12-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 15 [patent_no_of_words] => 4576 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 211 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/548/05548744.pdf [firstpage_image] =>[orig_patent_app_number] => 354934 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/354934
Memory circuit and method for setting an operation mode Dec 11, 1994 Issued
Array ( [id] => 3681634 [patent_doc_number] => 05600810 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-02-04 [patent_title] => 'Scaleable very long instruction word processor with parallelism matching' [patent_app_type] => 1 [patent_app_number] => 8/352927 [patent_app_country] => US [patent_app_date] => 1994-12-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 21 [patent_figures_cnt] => 24 [patent_no_of_words] => 7916 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 88 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/600/05600810.pdf [firstpage_image] =>[orig_patent_app_number] => 352927 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/352927
Scaleable very long instruction word processor with parallelism matching Dec 8, 1994 Issued
Array ( [id] => 3561741 [patent_doc_number] => 05546588 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-08-13 [patent_title] => 'Method and apparatus for preventing a data processing system from entering a non-recoverable state' [patent_app_type] => 1 [patent_app_number] => 8/350396 [patent_app_country] => US [patent_app_date] => 1994-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4685 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 144 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/546/05546588.pdf [firstpage_image] =>[orig_patent_app_number] => 350396 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/350396
Method and apparatus for preventing a data processing system from entering a non-recoverable state Dec 4, 1994 Issued
Array ( [id] => 3672814 [patent_doc_number] => 05592655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1997-01-07 [patent_title] => 'Logic simulation method' [patent_app_type] => 1 [patent_app_number] => 8/341115 [patent_app_country] => US [patent_app_date] => 1994-11-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 21 [patent_no_of_words] => 7945 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 114 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/592/05592655.pdf [firstpage_image] =>[orig_patent_app_number] => 341115 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/341115
Logic simulation method Nov 17, 1994 Issued
Array ( [id] => 3871248 [patent_doc_number] => 05706478 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1998-01-06 [patent_title] => 'Display list processor for operating in processor and coprocessor modes' [patent_app_type] => 1 [patent_app_number] => 8/338341 [patent_app_country] => US [patent_app_date] => 1994-11-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 16 [patent_no_of_words] => 11907 [patent_no_of_claims] => 24 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 87 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/706/05706478.pdf [firstpage_image] =>[orig_patent_app_number] => 338341 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/338341
Display list processor for operating in processor and coprocessor modes Nov 13, 1994 Issued
Array ( [id] => 3501472 [patent_doc_number] => 05471596 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-11-28 [patent_title] => 'Computer memory device holding a data structure for implementation of function objects' [patent_app_type] => 1 [patent_app_number] => 8/338267 [patent_app_country] => US [patent_app_date] => 1994-11-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 9432 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 32 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/471/05471596.pdf [firstpage_image] =>[orig_patent_app_number] => 338267 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/338267
Computer memory device holding a data structure for implementation of function objects Nov 9, 1994 Issued
Array ( [id] => 3592786 [patent_doc_number] => 05499373 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-03-12 [patent_title] => 'Apparatus and methods for designing, analyzing or simulating signal processing functions' [patent_app_type] => 1 [patent_app_number] => 8/337150 [patent_app_country] => US [patent_app_date] => 1994-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 10122 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 188 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/499/05499373.pdf [firstpage_image] =>[orig_patent_app_number] => 337150 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/337150
Apparatus and methods for designing, analyzing or simulating signal processing functions Nov 8, 1994 Issued
Array ( [id] => 3435025 [patent_doc_number] => 05459845 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1995-10-17 [patent_title] => 'Instruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completed' [patent_app_type] => 1 [patent_app_number] => 8/336326 [patent_app_country] => US [patent_app_date] => 1994-11-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 16 [patent_no_of_words] => 9862 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/459/05459845.pdf [firstpage_image] =>[orig_patent_app_number] => 336326 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/336326
Instruction pipeline sequencer in which state information of an instruction travels through pipe stages until the instruction execution is completed Nov 7, 1994 Issued
Array ( [id] => 3626126 [patent_doc_number] => 05535347 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1996-07-09 [patent_title] => 'Rotators in machine instruction length calculation' [patent_app_type] => 1 [patent_app_number] => 8/335305 [patent_app_country] => US [patent_app_date] => 1994-11-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 4510 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/05/535/05535347.pdf [firstpage_image] =>[orig_patent_app_number] => 335305 [rel_patent_id] =>[rel_patent_doc_number] =>)
08/335305
Rotators in machine instruction length calculation Nov 6, 1994 Issued
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