Search

Archie E. Williams Jr.

Examiner (ID: 11265)

Most Active Art Unit
2302
Art Unit(s)
2302, 2307
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2162264 [patent_doc_number] => 04525777 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-06-25 [patent_title] => 'Split-cycle cache system with SCU controlled cache clearing during cache store access period' [patent_app_type] => 1 [patent_app_number] => 6/289663 [patent_app_country] => US [patent_app_date] => 1981-08-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 5464 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/525/04525777.pdf [firstpage_image] =>[orig_patent_app_number] => 289663 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/289663
Split-cycle cache system with SCU controlled cache clearing during cache store access period Aug 2, 1981 Issued
Array ( [id] => 2063604 [patent_doc_number] => 04433390 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-21 [patent_title] => 'Power processing reset system for a microprocessor responding to sudden deregulation of a voltage' [patent_app_type] => 1 [patent_app_number] => 6/288591 [patent_app_country] => US [patent_app_date] => 1981-07-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3062 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 194 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/433/04433390.pdf [firstpage_image] =>[orig_patent_app_number] => 288591 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/288591
Power processing reset system for a microprocessor responding to sudden deregulation of a voltage Jul 29, 1981 Issued
Array ( [id] => 2082486 [patent_doc_number] => 04485497 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-04 [patent_title] => 'Apparatus for controlling re-distribution of load on continuous rolling mill' [patent_app_type] => 1 [patent_app_number] => 6/287761 [patent_app_country] => US [patent_app_date] => 1981-07-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5668 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 252 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/485/04485497.pdf [firstpage_image] =>[orig_patent_app_number] => 287761 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/287761
Apparatus for controlling re-distribution of load on continuous rolling mill Jul 27, 1981 Issued
Array ( [id] => 2130203 [patent_doc_number] => 04482949 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-13 [patent_title] => 'Unit for prioritizing earlier and later arriving input requests' [patent_app_type] => 1 [patent_app_number] => 6/284757 [patent_app_country] => US [patent_app_date] => 1981-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2491 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 132 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/482/04482949.pdf [firstpage_image] =>[orig_patent_app_number] => 284757 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/284757
Unit for prioritizing earlier and later arriving input requests Jul 19, 1981 Issued
Array ( [id] => 2157975 [patent_doc_number] => 04517661 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-05-14 [patent_title] => 'Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit' [patent_app_type] => 1 [patent_app_number] => 6/283778 [patent_app_country] => US [patent_app_date] => 1981-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 14 [patent_no_of_words] => 4319 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 196 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/517/04517661.pdf [firstpage_image] =>[orig_patent_app_number] => 283778 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/283778
Programmable chip tester having plural pin unit buffers which each store sufficient test data for independent operations by each pin unit Jul 15, 1981 Issued
06/281108 PROCESS FOR ACCELERATED ARBITRATION OF SEVERAL INDIVIDUAL PROCESSING UNITS AND AN ARBITRATION DEVICE FOR OPERATING THE SYSTEM Jul 6, 1981 Abandoned
Array ( [id] => 2125328 [patent_doc_number] => 04481604 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-06 [patent_title] => 'Postal meter using microcomputer scanning of encoding switches for simultaneous setting of electronic accounting & mechanical printing systems' [patent_app_type] => 1 [patent_app_number] => 6/280871 [patent_app_country] => US [patent_app_date] => 1981-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 20 [patent_no_of_words] => 9988 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 593 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/481/04481604.pdf [firstpage_image] =>[orig_patent_app_number] => 280871 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/280871
Postal meter using microcomputer scanning of encoding switches for simultaneous setting of electronic accounting & mechanical printing systems Jul 5, 1981 Issued
Array ( [id] => 2092123 [patent_doc_number] => 04476524 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-09 [patent_title] => 'Page storage control methods and means' [patent_app_type] => 1 [patent_app_number] => 6/279907 [patent_app_country] => US [patent_app_date] => 1981-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 10627 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 204 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/476/04476524.pdf [firstpage_image] =>[orig_patent_app_number] => 279907 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/279907
Page storage control methods and means Jul 1, 1981 Issued
Array ( [id] => 2203252 [patent_doc_number] => 04495594 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-22 [patent_title] => 'Synchronization of CRT controller chips' [patent_app_type] => 1 [patent_app_number] => 6/279368 [patent_app_country] => US [patent_app_date] => 1981-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 1812 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/495/04495594.pdf [firstpage_image] =>[orig_patent_app_number] => 279368 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/279368
Synchronization of CRT controller chips Jun 30, 1981 Issued
Array ( [id] => 2106383 [patent_doc_number] => 04442493 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-10 [patent_title] => 'Cutting tool retreat and return for workpiece protection upon abnormality occurrence in a preprogrammed machine tool' [patent_app_type] => 1 [patent_app_number] => 6/279033 [patent_app_country] => US [patent_app_date] => 1981-06-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 16 [patent_no_of_words] => 4754 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 125 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/442/04442493.pdf [firstpage_image] =>[orig_patent_app_number] => 279033 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/279033
Cutting tool retreat and return for workpiece protection upon abnormality occurrence in a preprogrammed machine tool Jun 29, 1981 Issued
Array ( [id] => 2203356 [patent_doc_number] => 04503491 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-05 [patent_title] => 'Computer with expanded addressing capability' [patent_app_type] => 1 [patent_app_number] => 6/278840 [patent_app_country] => US [patent_app_date] => 1981-06-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 6283 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 342 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/503/04503491.pdf [firstpage_image] =>[orig_patent_app_number] => 278840 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/278840
Computer with expanded addressing capability Jun 28, 1981 Issued
06/277006 PROCEDURE AND APPARATUS FOR INTER-PROCESSOR DATA TRANSFER IN A MULTI-PROCESSER SYSTEM Jun 23, 1981 Abandoned
Array ( [id] => 2115692 [patent_doc_number] => 04451897 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-29 [patent_title] => 'Control device with mode flags for dedicating memory segments as either scratchpad or timing control registers' [patent_app_type] => 1 [patent_app_number] => 6/274808 [patent_app_country] => US [patent_app_date] => 1981-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 24 [patent_no_of_words] => 8617 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/451/04451897.pdf [firstpage_image] =>[orig_patent_app_number] => 274808 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/274808
Control device with mode flags for dedicating memory segments as either scratchpad or timing control registers Jun 17, 1981 Issued
Array ( [id] => 2080993 [patent_doc_number] => 04445193 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-24 [patent_title] => 'Bisynchronous host/terminal communication system with non-clock-generating modem & PLL generated clock signal' [patent_app_type] => 1 [patent_app_number] => 6/274296 [patent_app_country] => US [patent_app_date] => 1981-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 17 [patent_no_of_words] => 2761 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 131 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/445/04445193.pdf [firstpage_image] =>[orig_patent_app_number] => 274296 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/274296
Bisynchronous host/terminal communication system with non-clock-generating modem & PLL generated clock signal Jun 15, 1981 Issued
Array ( [id] => 2098573 [patent_doc_number] => 04456954 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-06-26 [patent_title] => 'Virtual machine system with guest architecture emulation using hardware TLB\'s for plural level address translations' [patent_app_type] => 1 [patent_app_number] => 6/273532 [patent_app_country] => US [patent_app_date] => 1981-06-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 20 [patent_no_of_words] => 12645 [patent_no_of_claims] => 25 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/456/04456954.pdf [firstpage_image] =>[orig_patent_app_number] => 273532 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/273532
Virtual machine system with guest architecture emulation using hardware TLB's for plural level address translations Jun 14, 1981 Issued
Array ( [id] => 2183172 [patent_doc_number] => 04530068 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-16 [patent_title] => 'Electronic hand-held memory device' [patent_app_type] => 1 [patent_app_number] => 6/273103 [patent_app_country] => US [patent_app_date] => 1981-06-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 4590 [patent_no_of_claims] => 3 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 280 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/530/04530068.pdf [firstpage_image] =>[orig_patent_app_number] => 273103 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/273103
Electronic hand-held memory device Jun 11, 1981 Issued
Array ( [id] => 2089848 [patent_doc_number] => 04438489 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-20 [patent_title] => 'Interrupt pre-processor with dynamic allocation of priority levels to requests queued in an associative CAM' [patent_app_type] => 1 [patent_app_number] => 6/272606 [patent_app_country] => US [patent_app_date] => 1981-06-11 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5319 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 429 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/438/04438489.pdf [firstpage_image] =>[orig_patent_app_number] => 272606 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/272606
Interrupt pre-processor with dynamic allocation of priority levels to requests queued in an associative CAM Jun 10, 1981 Issued
Array ( [id] => 2121196 [patent_doc_number] => 04489378 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-18 [patent_title] => 'Automatic adjustment of the quantity of prefetch data in a disk cache operation' [patent_app_type] => 1 [patent_app_number] => 6/270750 [patent_app_country] => US [patent_app_date] => 1981-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 26 [patent_no_of_words] => 17527 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 81 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/489/04489378.pdf [firstpage_image] =>[orig_patent_app_number] => 270750 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/270750
Automatic adjustment of the quantity of prefetch data in a disk cache operation Jun 4, 1981 Issued
Array ( [id] => 2131881 [patent_doc_number] => 04490782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-25 [patent_title] => 'I/O Storage controller cache system with prefetch determined by requested record\'s position within data block' [patent_app_type] => 1 [patent_app_number] => 6/270951 [patent_app_country] => US [patent_app_date] => 1981-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 31 [patent_no_of_words] => 18011 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/490/04490782.pdf [firstpage_image] =>[orig_patent_app_number] => 270951 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/270951
I/O Storage controller cache system with prefetch determined by requested record's position within data block Jun 4, 1981 Issued
Array ( [id] => 2162641 [patent_doc_number] => 04525800 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-06-25 [patent_title] => 'Enhanced reliability data storage system with second memory for preserving time-dependent progressively updated data from destructive transient conditions' [patent_app_type] => 1 [patent_app_number] => 6/269102 [patent_app_country] => US [patent_app_date] => 1981-06-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 10287 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 206 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/525/04525800.pdf [firstpage_image] =>[orig_patent_app_number] => 269102 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/269102
Enhanced reliability data storage system with second memory for preserving time-dependent progressively updated data from destructive transient conditions May 31, 1981 Issued
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