Search

Archie E. Williams Jr.

Examiner (ID: 11265)

Most Active Art Unit
2302
Art Unit(s)
2302, 2307
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2106584 [patent_doc_number] => 04446516 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-01 [patent_title] => 'Data compaction system with contiguous storage of non-redundant information and run length counts' [patent_app_type] => 1 [patent_app_number] => 6/247265 [patent_app_country] => US [patent_app_date] => 1981-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 3933 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/446/04446516.pdf [firstpage_image] =>[orig_patent_app_number] => 247265 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/247265
Data compaction system with contiguous storage of non-redundant information and run length counts Mar 24, 1981 Issued
Array ( [id] => 2180948 [patent_doc_number] => 04513174 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-04-23 [patent_title] => 'Software security method using partial fabrication of proprietary control word decoders and microinstruction memories' [patent_app_type] => 1 [patent_app_number] => 6/245498 [patent_app_country] => US [patent_app_date] => 1981-03-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 2770 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/513/04513174.pdf [firstpage_image] =>[orig_patent_app_number] => 245498 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/245498
Software security method using partial fabrication of proprietary control word decoders and microinstruction memories Mar 18, 1981 Issued
Array ( [id] => 2092107 [patent_doc_number] => 04476522 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-10-09 [patent_title] => 'Programmable peripheral processing controller with mode-selectable address register sequencing' [patent_app_type] => 1 [patent_app_number] => 6/241902 [patent_app_country] => US [patent_app_date] => 1981-03-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6049 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 182 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/476/04476522.pdf [firstpage_image] =>[orig_patent_app_number] => 241902 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/241902
Programmable peripheral processing controller with mode-selectable address register sequencing Mar 8, 1981 Issued
Array ( [id] => 2042959 [patent_doc_number] => 04413328 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-11-01 [patent_title] => 'Storage subsystems employing removable media and having a digital display on each recorder' [patent_app_type] => 1 [patent_app_number] => 6/241168 [patent_app_country] => US [patent_app_date] => 1981-03-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 10152 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/413/04413328.pdf [firstpage_image] =>[orig_patent_app_number] => 241168 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/241168
Storage subsystems employing removable media and having a digital display on each recorder Mar 5, 1981 Issued
06/235864 SHIFT MATRIX PRESELECTOR CONTROL CIRCUIT Feb 18, 1981 Abandoned
Array ( [id] => 2160590 [patent_doc_number] => 04519028 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-05-21 [patent_title] => 'CPU with multi-stage mode register for defining CPU operating environment including charging its communications protocol' [patent_app_type] => 1 [patent_app_number] => 6/234926 [patent_app_country] => US [patent_app_date] => 1981-02-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 35 [patent_no_of_words] => 12900 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 174 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/519/04519028.pdf [firstpage_image] =>[orig_patent_app_number] => 234926 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/234926
CPU with multi-stage mode register for defining CPU operating environment including charging its communications protocol Feb 16, 1981 Issued
Array ( [id] => 2065365 [patent_doc_number] => 04428042 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-01-24 [patent_title] => 'Interface device for coupling a system of time-division multiplexed channels to a data concentrator' [patent_app_type] => 1 [patent_app_number] => 6/231455 [patent_app_country] => US [patent_app_date] => 1981-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 11 [patent_no_of_words] => 6975 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 338 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/428/04428042.pdf [firstpage_image] =>[orig_patent_app_number] => 231455 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/231455
Interface device for coupling a system of time-division multiplexed channels to a data concentrator Feb 3, 1981 Issued
Array ( [id] => 1975844 [patent_doc_number] => 04354252 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-10-12 [patent_title] => 'Programmable digital data terminal for mobile radio transceivers' [patent_app_type] => 1 [patent_app_number] => 6/230828 [patent_app_country] => US [patent_app_date] => 1981-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 18 [patent_figures_cnt] => 18 [patent_no_of_words] => 13273 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 162 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/354/04354252.pdf [firstpage_image] =>[orig_patent_app_number] => 230828 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/230828
Programmable digital data terminal for mobile radio transceivers Feb 1, 1981 Issued
Array ( [id] => 1987916 [patent_doc_number] => 04360880 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-11-23 [patent_title] => 'Recirculating RMS AC conversion method and apparatus with fast mode' [patent_app_type] => 1 [patent_app_number] => 6/228081 [patent_app_country] => US [patent_app_date] => 1981-01-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 5368 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/360/04360880.pdf [firstpage_image] =>[orig_patent_app_number] => 228081 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/228081
Recirculating RMS AC conversion method and apparatus with fast mode Jan 25, 1981 Issued
Array ( [id] => 1997716 [patent_doc_number] => 04381553 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-04-26 [patent_title] => 'Programmable printer controller with multiline buffering and overstrike feature' [patent_app_type] => 1 [patent_app_number] => 6/227281 [patent_app_country] => US [patent_app_date] => 1981-01-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 5104 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 44 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/381/04381553.pdf [firstpage_image] =>[orig_patent_app_number] => 227281 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/227281
Programmable printer controller with multiline buffering and overstrike feature Jan 21, 1981 Issued
Array ( [id] => 2108421 [patent_doc_number] => 04484261 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-20 [patent_title] => 'Data processing system having interlinked fast and slow memory means and interlinked program counters' [patent_app_type] => 1 [patent_app_number] => 6/221417 [patent_app_country] => US [patent_app_date] => 1981-01-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 51 [patent_figures_cnt] => 59 [patent_no_of_words] => 21683 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/484/04484261.pdf [firstpage_image] =>[orig_patent_app_number] => 221417 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/221417
Data processing system having interlinked fast and slow memory means and interlinked program counters Jan 18, 1981 Issued
Array ( [id] => 2119324 [patent_doc_number] => 04439865 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-27 [patent_title] => 'Copier sorter with memory and counter controlled inlet gate for manually inserted covers or partition sheets' [patent_app_type] => 1 [patent_app_number] => 6/223168 [patent_app_country] => US [patent_app_date] => 1981-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 47 [patent_figures_cnt] => 53 [patent_no_of_words] => 25340 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 339 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/439/04439865.pdf [firstpage_image] =>[orig_patent_app_number] => 223168 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/223168
Copier sorter with memory and counter controlled inlet gate for manually inserted covers or partition sheets Jan 6, 1981 Issued
Array ( [id] => 2133390 [patent_doc_number] => 04454575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-06-12 [patent_title] => 'Shared memory system with access by specialized peripherals managed by controller initialized by supervisory CPU' [patent_app_type] => 1 [patent_app_number] => 6/220637 [patent_app_country] => US [patent_app_date] => 1980-12-29 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 19 [patent_no_of_words] => 13810 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 155 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/454/04454575.pdf [firstpage_image] =>[orig_patent_app_number] => 220637 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/220637
Shared memory system with access by specialized peripherals managed by controller initialized by supervisory CPU Dec 28, 1980 Issued
Array ( [id] => 2118784 [patent_doc_number] => 04437166 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-13 [patent_title] => 'High speed byte shifter for a bi-directional data bus' [patent_app_type] => 1 [patent_app_number] => 6/219768 [patent_app_country] => US [patent_app_date] => 1980-12-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 6250 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 140 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/437/04437166.pdf [firstpage_image] =>[orig_patent_app_number] => 219768 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/219768
High speed byte shifter for a bi-directional data bus Dec 22, 1980 Issued
Array ( [id] => 2271128 [patent_doc_number] => 04575816 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-11 [patent_title] => 'Interactive transactions processor using sequence table pointers to access function table statements controlling execution of specific interactive functions' [patent_app_type] => 1 [patent_app_number] => 6/218143 [patent_app_country] => US [patent_app_date] => 1980-12-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6298 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 126 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/575/04575816.pdf [firstpage_image] =>[orig_patent_app_number] => 218143 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/218143
Interactive transactions processor using sequence table pointers to access function table statements controlling execution of specific interactive functions Dec 18, 1980 Issued
Array ( [id] => 2198108 [patent_doc_number] => 04502110 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-02-26 [patent_title] => 'Split-cache having equal size operand and instruction memories' [patent_app_type] => 1 [patent_app_number] => 6/214932 [patent_app_country] => US [patent_app_date] => 1980-12-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 25 [patent_no_of_words] => 4428 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/502/04502110.pdf [firstpage_image] =>[orig_patent_app_number] => 214932 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/214932
Split-cache having equal size operand and instruction memories Dec 9, 1980 Issued
Array ( [id] => 2106305 [patent_doc_number] => 04442485 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-10 [patent_title] => 'Dynamically buffered data transfer system for large capacity data source' [patent_app_type] => 1 [patent_app_number] => 6/213403 [patent_app_country] => US [patent_app_date] => 1980-12-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 3170 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 209 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/442/04442485.pdf [firstpage_image] =>[orig_patent_app_number] => 213403 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/213403
Dynamically buffered data transfer system for large capacity data source Dec 4, 1980 Issued
Array ( [id] => 2082682 [patent_doc_number] => 04434463 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-02-28 [patent_title] => 'Multiprocessor topology with plural bases for directly and indirectly coupling addresses and relay stations' [patent_app_type] => 1 [patent_app_number] => 6/210819 [patent_app_country] => US [patent_app_date] => 1980-11-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 17 [patent_no_of_words] => 6693 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 295 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/434/04434463.pdf [firstpage_image] =>[orig_patent_app_number] => 210819 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/210819
Multiprocessor topology with plural bases for directly and indirectly coupling addresses and relay stations Nov 25, 1980 Issued
Array ( [id] => 2086545 [patent_doc_number] => 04450519 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-05-22 [patent_title] => 'Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories' [patent_app_type] => 1 [patent_app_number] => 6/210106 [patent_app_country] => US [patent_app_date] => 1980-11-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 32 [patent_figures_cnt] => 9 [patent_no_of_words] => 8707 [patent_no_of_claims] => 16 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 208 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/450/04450519.pdf [firstpage_image] =>[orig_patent_app_number] => 210106 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/210106
Psuedo-microprogramming in microprocessor in single-chip microprocessor with alternate IR loading from internal or external program memories Nov 23, 1980 Issued
Array ( [id] => 2108828 [patent_doc_number] => 04484302 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-20 [patent_title] => 'Single screen display system with multiple virtual display having prioritized service programs and dedicated memory stacks' [patent_app_type] => 1 [patent_app_number] => 6/208817 [patent_app_country] => US [patent_app_date] => 1980-11-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 5659 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/484/04484302.pdf [firstpage_image] =>[orig_patent_app_number] => 208817 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/208817
Single screen display system with multiple virtual display having prioritized service programs and dedicated memory stacks Nov 19, 1980 Issued
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