Search

Archie E. Williams Jr.

Examiner (ID: 11265)

Most Active Art Unit
2302
Art Unit(s)
2302, 2307
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2132182 [patent_doc_number] => 04490809 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-25 [patent_title] => 'Multichip data shifting system' [patent_app_type] => 1 [patent_app_number] => 6/180454 [patent_app_country] => US [patent_app_date] => 1980-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 22 [patent_no_of_words] => 4588 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/490/04490809.pdf [firstpage_image] =>[orig_patent_app_number] => 180454 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/180454
Multichip data shifting system Aug 21, 1980 Issued
Array ( [id] => 2184780 [patent_doc_number] => 04509137 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-04-02 [patent_title] => 'Language translator with random generation of test words during learning mode' [patent_app_type] => 1 [patent_app_number] => 6/176294 [patent_app_country] => US [patent_app_date] => 1980-08-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3750 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 411 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/509/04509137.pdf [firstpage_image] =>[orig_patent_app_number] => 176294 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/176294
Language translator with random generation of test words during learning mode Aug 7, 1980 Issued
Array ( [id] => 2113041 [patent_doc_number] => 04467409 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-21 [patent_title] => 'Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations' [patent_app_type] => 1 [patent_app_number] => 6/175430 [patent_app_country] => US [patent_app_date] => 1980-08-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 7485 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 147 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/467/04467409.pdf [firstpage_image] =>[orig_patent_app_number] => 175430 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/175430
Flexible computer architecture using arrays of standardized microprocessors customized for pipeline and parallel operations Aug 4, 1980 Issued
Array ( [id] => 2024235 [patent_doc_number] => 04370709 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-01-25 [patent_title] => 'Computer emulator with three segment microcode memory and two separate microcontrollers for operand derivation and execution phases' [patent_app_type] => 1 [patent_app_number] => 6/174721 [patent_app_country] => US [patent_app_date] => 1980-08-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 22 [patent_figures_cnt] => 25 [patent_no_of_words] => 28316 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 30 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/370/04370709.pdf [firstpage_image] =>[orig_patent_app_number] => 174721 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/174721
Computer emulator with three segment microcode memory and two separate microcontrollers for operand derivation and execution phases Jul 31, 1980 Issued
06/169250 PARALLEL PRIORITY AND LOGICAL LOCATION RESOLUTION IN A DISTRIBUTED PROCESSING SYSTEM Jul 15, 1980 Abandoned
Array ( [id] => 2041218 [patent_doc_number] => 04410939 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-18 [patent_title] => 'System for program interrupt processing with quasi-stack of register-sets' [patent_app_type] => 1 [patent_app_number] => 6/169475 [patent_app_country] => US [patent_app_date] => 1980-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 8 [patent_no_of_words] => 6381 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 292 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/410/04410939.pdf [firstpage_image] =>[orig_patent_app_number] => 169475 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/169475
System for program interrupt processing with quasi-stack of register-sets Jul 15, 1980 Issued
Array ( [id] => 2130357 [patent_doc_number] => 04482965 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-13 [patent_title] => 'Taximeter with tariff display mode controlled by removable memory addressable by fare rate keys' [patent_app_type] => 1 [patent_app_number] => 6/165338 [patent_app_country] => US [patent_app_date] => 1980-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 4 [patent_no_of_words] => 2838 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 228 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/482/04482965.pdf [firstpage_image] =>[orig_patent_app_number] => 165338 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/165338
Taximeter with tariff display mode controlled by removable memory addressable by fare rate keys Jul 1, 1980 Issued
Array ( [id] => 2021422 [patent_doc_number] => 04403301 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-09-06 [patent_title] => 'Word processor adapted for filling in blanks on preprinted forms' [patent_app_type] => 1 [patent_app_number] => 6/164516 [patent_app_country] => US [patent_app_date] => 1980-07-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 2540 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/403/04403301.pdf [firstpage_image] =>[orig_patent_app_number] => 164516 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/164516
Word processor adapted for filling in blanks on preprinted forms Jul 1, 1980 Issued
Array ( [id] => 2136484 [patent_doc_number] => 04516218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-05-07 [patent_title] => 'Memory system with single command selective sequential accessing of predetermined pluralities of data locations' [patent_app_type] => 1 [patent_app_number] => 6/163025 [patent_app_country] => US [patent_app_date] => 1980-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 46 [patent_figures_cnt] => 52 [patent_no_of_words] => 13531 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 239 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/516/04516218.pdf [firstpage_image] =>[orig_patent_app_number] => 163025 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/163025
Memory system with single command selective sequential accessing of predetermined pluralities of data locations Jun 25, 1980 Issued
Array ( [id] => 2089837 [patent_doc_number] => 04438488 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-03-20 [patent_title] => 'Data processing system with a slave computer using data registers as the sole operand store' [patent_app_type] => 1 [patent_app_number] => 6/160490 [patent_app_country] => US [patent_app_date] => 1980-06-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 12 [patent_no_of_words] => 5583 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 268 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/438/04438488.pdf [firstpage_image] =>[orig_patent_app_number] => 160490 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/160490
Data processing system with a slave computer using data registers as the sole operand store Jun 17, 1980 Issued
Array ( [id] => 2097414 [patent_doc_number] => 04443860 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-04-17 [patent_title] => 'System for hi-speed comparisons between variable format input data and stored tabular reference data' [patent_app_type] => 1 [patent_app_number] => 6/158318 [patent_app_country] => US [patent_app_date] => 1980-06-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 11 [patent_no_of_words] => 11774 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 597 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/443/04443860.pdf [firstpage_image] =>[orig_patent_app_number] => 158318 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/158318
System for hi-speed comparisons between variable format input data and stored tabular reference data Jun 9, 1980 Issued
Array ( [id] => 2033235 [patent_doc_number] => 04382278 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-05-03 [patent_title] => 'Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache' [patent_app_type] => 1 [patent_app_number] => 6/156723 [patent_app_country] => US [patent_app_date] => 1980-06-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 7 [patent_no_of_words] => 2704 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/382/04382278.pdf [firstpage_image] =>[orig_patent_app_number] => 156723 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/156723
Hierarchial memory system with microcommand memory and pointer register mapping virtual CPU registers in workspace cache #4 and main memory cache Jun 4, 1980 Issued
06/155152 MICROPROCESSOR WITH IMPROVED INFORMATION BUS UTILIZATION May 29, 1980 Abandoned
Array ( [id] => 2166819 [patent_doc_number] => 04500952 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-02-19 [patent_title] => 'Mechanism for control of address translation by a program using a plurality of translation tables' [patent_app_type] => 1 [patent_app_number] => 6/152889 [patent_app_country] => US [patent_app_date] => 1980-05-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 17 [patent_no_of_words] => 12307 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 73 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/500/04500952.pdf [firstpage_image] =>[orig_patent_app_number] => 152889 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/152889
Mechanism for control of address translation by a program using a plurality of translation tables May 22, 1980 Issued
Array ( [id] => 2047735 [patent_doc_number] => 04387294 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-06-07 [patent_title] => 'Shift register-latch circuit driven by clocks with half cycle phase deviation and usable with a serial alu' [patent_app_type] => 1 [patent_app_number] => 6/147078 [patent_app_country] => US [patent_app_date] => 1980-05-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3586 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 181 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/387/04387294.pdf [firstpage_image] =>[orig_patent_app_number] => 147078 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/147078
Shift register-latch circuit driven by clocks with half cycle phase deviation and usable with a serial alu May 6, 1980 Issued
Array ( [id] => 2021064 [patent_doc_number] => 04371929 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-02-01 [patent_title] => 'Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory' [patent_app_type] => 1 [patent_app_number] => 6/146897 [patent_app_country] => US [patent_app_date] => 1980-05-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 13 [patent_no_of_words] => 10992 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 231 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/371/04371929.pdf [firstpage_image] =>[orig_patent_app_number] => 146897 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/146897
Multiprocessor system with high density memory set architecture including partitionable cache store interface to shared disk drive memory May 4, 1980 Issued
Array ( [id] => 2120551 [patent_doc_number] => 04468732 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-28 [patent_title] => 'Automated logical file design system with reduced data base redundancy' [patent_app_type] => 1 [patent_app_number] => 6/144116 [patent_app_country] => US [patent_app_date] => 1980-04-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 25 [patent_no_of_words] => 12990 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 282 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/468/04468732.pdf [firstpage_image] =>[orig_patent_app_number] => 144116 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/144116
Automated logical file design system with reduced data base redundancy Apr 27, 1980 Issued
Array ( [id] => 2063673 [patent_doc_number] => 04409655 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-10-11 [patent_title] => 'Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses' [patent_app_type] => 1 [patent_app_number] => 6/143981 [patent_app_country] => US [patent_app_date] => 1980-04-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 1422 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 254 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/409/04409655.pdf [firstpage_image] =>[orig_patent_app_number] => 143981 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/143981
Hierarchial memory ring protection system using comparisons of requested and previously accessed addresses Apr 24, 1980 Issued
Array ( [id] => 1934744 [patent_doc_number] => 04347582 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1982-08-31 [patent_title] => 'Central timer unit for buffering control data in a telecommunications system' [patent_app_type] => 1 [patent_app_number] => 6/143159 [patent_app_country] => US [patent_app_date] => 1980-04-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 1 [patent_no_of_words] => 8577 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 355 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/347/04347582.pdf [firstpage_image] =>[orig_patent_app_number] => 143159 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/143159
Central timer unit for buffering control data in a telecommunications system Apr 22, 1980 Issued
Array ( [id] => 2055473 [patent_doc_number] => 04390969 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-06-28 [patent_title] => 'Asynchronous data transmission system with state variable memory and handshaking protocol circuits' [patent_app_type] => 1 [patent_app_number] => 6/142608 [patent_app_country] => US [patent_app_date] => 1980-04-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 6 [patent_no_of_words] => 2593 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 151 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/390/04390969.pdf [firstpage_image] =>[orig_patent_app_number] => 142608 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/142608
Asynchronous data transmission system with state variable memory and handshaking protocol circuits Apr 20, 1980 Issued
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