Search

Archie E. Williams Jr.

Examiner (ID: 1028)

Most Active Art Unit
2302
Art Unit(s)
2307, 2302
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2324965 [patent_doc_number] => 04689768 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-08-25 [patent_title] => 'Spelling verification system with immediate operator alerts to non-matches between inputted words and words stored in plural dictionary memories' [patent_app_type] => 1 [patent_app_number] => 6/820905 [patent_app_country] => US [patent_app_date] => 1986-01-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 4229 [patent_no_of_claims] => 22 [patent_no_of_ind_claims] => 7 [patent_words_short_claim] => 197 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/689/04689768.pdf [firstpage_image] =>[orig_patent_app_number] => 820905 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/820905
Spelling verification system with immediate operator alerts to non-matches between inputted words and words stored in plural dictionary memories Jan 15, 1986 Issued
06/792270 METHOD AND APPARATUS FOR NATURAL LANGUAGE PROCESSING Oct 27, 1985 Abandoned
Array ( [id] => 2286526 [patent_doc_number] => 04626985 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-02 [patent_title] => 'Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus' [patent_app_type] => 1 [patent_app_number] => 6/783261 [patent_app_country] => US [patent_app_date] => 1985-10-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 3171 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 245 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/626/04626985.pdf [firstpage_image] =>[orig_patent_app_number] => 783261 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/783261
Single-chip microcomputer with internal time-multiplexed address/data/interrupt bus Oct 2, 1985 Issued
06/767769 AERIAL DEVICE PROTECTION Aug 20, 1985 Abandoned
06/766942 INTERRUPT CONTROL SYSTEM Aug 18, 1985 Abandoned
Array ( [id] => 2252014 [patent_doc_number] => 04633435 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-30 [patent_title] => 'Electronic language translator capable of modifying definite articles or prepositions to correspond to modified related words' [patent_app_type] => 1 [patent_app_number] => 6/757206 [patent_app_country] => US [patent_app_date] => 1985-07-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 4899 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 410 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/633/04633435.pdf [firstpage_image] =>[orig_patent_app_number] => 757206 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/757206
Electronic language translator capable of modifying definite articles or prepositions to correspond to modified related words Jul 21, 1985 Issued
06/734930 SPELLING VERIFICATION METHOD FOR A TYPEWRITER AND TYPEWRITER EMBODYING SAID METHOD May 15, 1985 Abandoned
Array ( [id] => 2358566 [patent_doc_number] => 04654782 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-31 [patent_title] => 'Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs' [patent_app_type] => 1 [patent_app_number] => 6/728459 [patent_app_country] => US [patent_app_date] => 1985-05-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 5 [patent_no_of_words] => 1427 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 329 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/654/04654782.pdf [firstpage_image] =>[orig_patent_app_number] => 728459 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/728459
Variable segment size plural cache system with cache memory unit selection based on relative priorities of accessed encached programs Apr 30, 1985 Issued
Array ( [id] => 2247684 [patent_doc_number] => 04567575 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-01-28 [patent_title] => 'Voltage level compensating interface circuit for inter-logic circuit data transmission system' [patent_app_type] => 1 [patent_app_number] => 6/726933 [patent_app_country] => US [patent_app_date] => 1985-04-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 1846 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 244 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/567/04567575.pdf [firstpage_image] =>[orig_patent_app_number] => 726933 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/726933
Voltage level compensating interface circuit for inter-logic circuit data transmission system Apr 25, 1985 Issued
06/725700 COMPUTER-AIDED SOFTWARE ENGINEERING SYSTEM Apr 21, 1985 Abandoned
Array ( [id] => 2401556 [patent_doc_number] => 04769772 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-09-06 [patent_title] => 'Automated query optimization method using both global and parallel local optimizations for materialization access planning for distributed databases' [patent_app_type] => 1 [patent_app_number] => 6/706702 [patent_app_country] => US [patent_app_date] => 1985-02-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 17562 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 247 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/769/04769772.pdf [firstpage_image] =>[orig_patent_app_number] => 706702 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/706702
Automated query optimization method using both global and parallel local optimizations for materialization access planning for distributed databases Feb 27, 1985 Issued
Array ( [id] => 2430270 [patent_doc_number] => 04780813 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-10-25 [patent_title] => 'Data transport control apparatus' [patent_app_type] => 1 [patent_app_number] => 6/705457 [patent_app_country] => US [patent_app_date] => 1985-02-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 3258 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/780/04780813.pdf [firstpage_image] =>[orig_patent_app_number] => 705457 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/705457
Data transport control apparatus Feb 24, 1985 Issued
Array ( [id] => 2389999 [patent_doc_number] => 04783758 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-11-08 [patent_title] => 'Automated word substitution using numerical rankings of structural disparity between misspelled words & candidate substitution words' [patent_app_type] => 1 [patent_app_number] => 6/699202 [patent_app_country] => US [patent_app_date] => 1985-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 3 [patent_no_of_words] => 4599 [patent_no_of_claims] => 31 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 223 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/783/04783758.pdf [firstpage_image] =>[orig_patent_app_number] => 699202 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/699202
Automated word substitution using numerical rankings of structural disparity between misspelled words & candidate substitution words Feb 4, 1985 Issued
06/691775 INTELLIGENT ELECTRONIC WORD PROCESSOR Jan 15, 1985 Abandoned
Array ( [id] => 2153564 [patent_doc_number] => 04539636 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-09-03 [patent_title] => 'Apparatus for inter-processor data transfer in a multi-processor system' [patent_app_type] => 1 [patent_app_number] => 6/676599 [patent_app_country] => US [patent_app_date] => 1984-11-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 3 [patent_no_of_words] => 1972 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/539/04539636.pdf [firstpage_image] =>[orig_patent_app_number] => 676599 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/676599
Apparatus for inter-processor data transfer in a multi-processor system Nov 29, 1984 Issued
Array ( [id] => 2434103 [patent_doc_number] => 04739475 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-04-19 [patent_title] => 'Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability' [patent_app_type] => 1 [patent_app_number] => 6/675831 [patent_app_country] => US [patent_app_date] => 1984-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 16 [patent_figures_cnt] => 23 [patent_no_of_words] => 14570 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 465 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/739/04739475.pdf [firstpage_image] =>[orig_patent_app_number] => 675831 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/675831
Topography for sixteen bit CMOS microprocessor with eight bit emulation and abort capability Nov 27, 1984 Issued
Array ( [id] => 2164007 [patent_doc_number] => 04554628 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-19 [patent_title] => 'System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn\'t bid again until all stored bids win' [patent_app_type] => 1 [patent_app_number] => 6/670117 [patent_app_country] => US [patent_app_date] => 1984-11-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 8 [patent_no_of_words] => 4695 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 115 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/554/04554628.pdf [firstpage_image] =>[orig_patent_app_number] => 670117 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/670117
System in which multiple devices have a circuit that bids with a fixed priority, stores all losing bids if its bid wins, and doesn't bid again until all stored bids win Nov 8, 1984 Issued
06/669123 PARALLEL PROCESSING COMPUTER Nov 6, 1984 Abandoned
Array ( [id] => 2227106 [patent_doc_number] => 04628447 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-12-09 [patent_title] => 'Multi-level arbitration system for decentrally allocating resource priority among individual processing units' [patent_app_type] => 1 [patent_app_number] => 6/667391 [patent_app_country] => US [patent_app_date] => 1984-11-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 5271 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 401 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/628/04628447.pdf [firstpage_image] =>[orig_patent_app_number] => 667391 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/667391
Multi-level arbitration system for decentrally allocating resource priority among individual processing units Nov 1, 1984 Issued
06/659192 DOCUMENT MANAGER MEANS FOR A MULTI- TASKING DATA PROCESSING SYSTEM Oct 8, 1984 Abandoned
Menu