Search

Archie E. Williams Jr.

Examiner (ID: 11265)

Most Active Art Unit
2302
Art Unit(s)
2302, 2307
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2358648 [patent_doc_number] => 04654790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-31 [patent_title] => 'Translation of virtual and real addresses to system addresses' [patent_app_type] => 1 [patent_app_number] => 6/555901 [patent_app_country] => US [patent_app_date] => 1983-11-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4906 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 305 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/654/04654790.pdf [firstpage_image] =>[orig_patent_app_number] => 555901 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/555901
Translation of virtual and real addresses to system addresses Nov 27, 1983 Issued
06/554714 INTERFACE CIRCUIT Nov 22, 1983 Abandoned
Array ( [id] => 2393285 [patent_doc_number] => 04724517 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1988-02-09 [patent_title] => 'Microcomputer with prefixing functions' [patent_app_type] => 1 [patent_app_number] => 6/553029 [patent_app_country] => US [patent_app_date] => 1983-11-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 15 [patent_figures_cnt] => 23 [patent_no_of_words] => 22309 [patent_no_of_claims] => 41 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 135 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/724/04724517.pdf [firstpage_image] =>[orig_patent_app_number] => 553029 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/553029
Microcomputer with prefixing functions Nov 15, 1983 Issued
06/546588 PORTABLE MACHINE FOR CALCULATION OR DATA PROCESSING Oct 27, 1983 Abandoned
Array ( [id] => 2225615 [patent_doc_number] => 04594686 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-10 [patent_title] => 'Language interpreter for inflecting words from their uninflected forms' [patent_app_type] => 1 [patent_app_number] => 6/545216 [patent_app_country] => US [patent_app_date] => 1983-10-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 4778 [patent_no_of_claims] => 4 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 317 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/594/04594686.pdf [firstpage_image] =>[orig_patent_app_number] => 545216 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/545216
Language interpreter for inflecting words from their uninflected forms Oct 24, 1983 Issued
06/534720 RETRY MECHANISM FOR RELEASING CONTROL OF A COMMUNICATIONS PATH IN A DIGITAL COMPUTER SYSTEM Sep 21, 1983 Abandoned
Array ( [id] => 2364811 [patent_doc_number] => 04648030 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-03-03 [patent_title] => 'Cache invalidation mechanism for multiprocessor systems' [patent_app_type] => 1 [patent_app_number] => 6/534782 [patent_app_country] => US [patent_app_date] => 1983-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 17 [patent_figures_cnt] => 29 [patent_no_of_words] => 13566 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 157 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/648/04648030.pdf [firstpage_image] =>[orig_patent_app_number] => 534782 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/534782
Cache invalidation mechanism for multiprocessor systems Sep 21, 1983 Issued
Array ( [id] => 2347333 [patent_doc_number] => 04661905 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1987-04-28 [patent_title] => 'Bus-control mechanism' [patent_app_type] => 1 [patent_app_number] => 6/534781 [patent_app_country] => US [patent_app_date] => 1983-09-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 31 [patent_no_of_words] => 14187 [patent_no_of_claims] => 2 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 376 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/661/04661905.pdf [firstpage_image] =>[orig_patent_app_number] => 534781 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/534781
Bus-control mechanism Sep 21, 1983 Issued
Array ( [id] => 2145510 [patent_doc_number] => 04523276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-06-11 [patent_title] => 'Input/output control device with memory device for storing variable-length data and method of controlling thereof' [patent_app_type] => 1 [patent_app_number] => 6/533803 [patent_app_country] => US [patent_app_date] => 1983-09-19 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 19 [patent_no_of_words] => 6174 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 267 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/523/04523276.pdf [firstpage_image] =>[orig_patent_app_number] => 533803 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/533803
Input/output control device with memory device for storing variable-length data and method of controlling thereof Sep 18, 1983 Issued
Array ( [id] => 2223341 [patent_doc_number] => 04621343 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-04 [patent_title] => 'Circuit arrangement for detecting error in print control apparatus' [patent_app_type] => 1 [patent_app_number] => 6/526771 [patent_app_country] => US [patent_app_date] => 1983-08-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 10 [patent_no_of_words] => 3563 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 352 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/621/04621343.pdf [firstpage_image] =>[orig_patent_app_number] => 526771 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/526771
Circuit arrangement for detecting error in print control apparatus Aug 25, 1983 Issued
Array ( [id] => 2253436 [patent_doc_number] => 04606002 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-08-12 [patent_title] => 'B-tree structured data base using sparse array bit maps to store inverted lists' [patent_app_type] => 1 [patent_app_number] => 6/523527 [patent_app_country] => US [patent_app_date] => 1983-08-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 10 [patent_no_of_words] => 5263 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/606/04606002.pdf [firstpage_image] =>[orig_patent_app_number] => 523527 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/523527
B-tree structured data base using sparse array bit maps to store inverted lists Aug 16, 1983 Issued
Array ( [id] => 2265937 [patent_doc_number] => 04564901 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-01-14 [patent_title] => 'Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors' [patent_app_type] => 1 [patent_app_number] => 6/515852 [patent_app_country] => US [patent_app_date] => 1983-07-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 10868 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 180 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/564/04564901.pdf [firstpage_image] =>[orig_patent_app_number] => 515852 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/515852
Method of performing a sequence of related activities via multiple asynchronously intercoupled digital processors Jul 20, 1983 Issued
Array ( [id] => 2265831 [patent_doc_number] => 04598363 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-01 [patent_title] => 'Adaptive delayed polling of sensors' [patent_app_type] => 1 [patent_app_number] => 6/511742 [patent_app_country] => US [patent_app_date] => 1983-07-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5170 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 5 [patent_words_short_claim] => 120 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/598/04598363.pdf [firstpage_image] =>[orig_patent_app_number] => 511742 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/511742
Adaptive delayed polling of sensors Jul 6, 1983 Issued
Array ( [id] => 2120606 [patent_doc_number] => 04468738 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-08-28 [patent_title] => 'Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors' [patent_app_type] => 1 [patent_app_number] => 6/512564 [patent_app_country] => US [patent_app_date] => 1983-07-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 7385 [patent_no_of_claims] => 15 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 168 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/468/04468738.pdf [firstpage_image] =>[orig_patent_app_number] => 512564 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/512564
Bus access arbitration using unitary arithmetic resolution logic and unique logical addresses of competing processors Jul 4, 1983 Issued
Array ( [id] => 2291807 [patent_doc_number] => 04587609 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-05-06 [patent_title] => 'Lockout operation among asynchronous accessers of a shared computer system resource' [patent_app_type] => 1 [patent_app_number] => 6/510472 [patent_app_country] => US [patent_app_date] => 1983-07-01 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 10 [patent_no_of_words] => 19077 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 258 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/587/04587609.pdf [firstpage_image] =>[orig_patent_app_number] => 510472 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/510472
Lockout operation among asynchronous accessers of a shared computer system resource Jun 30, 1983 Issued
Array ( [id] => 2108556 [patent_doc_number] => 04484276 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-20 [patent_title] => 'Shift matrix preselector control circuit' [patent_app_type] => 1 [patent_app_number] => 6/509096 [patent_app_country] => US [patent_app_date] => 1983-06-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 11 [patent_no_of_words] => 12408 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 221 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/484/04484276.pdf [firstpage_image] =>[orig_patent_app_number] => 509096 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/509096
Shift matrix preselector control circuit Jun 27, 1983 Issued
Array ( [id] => 2265815 [patent_doc_number] => 04598362 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-07-01 [patent_title] => 'Buffer apparatus for controlling access requests among plural memories and plural accessing devices' [patent_app_type] => 1 [patent_app_number] => 6/506363 [patent_app_country] => US [patent_app_date] => 1983-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 7 [patent_no_of_words] => 5792 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 235 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/598/04598362.pdf [firstpage_image] =>[orig_patent_app_number] => 506363 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/506363
Buffer apparatus for controlling access requests among plural memories and plural accessing devices Jun 20, 1983 Issued
Array ( [id] => 2233871 [patent_doc_number] => 04571700 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-02-18 [patent_title] => 'Page indexing system for accessing sequentially stored data representing a multi-page document' [patent_app_type] => 1 [patent_app_number] => 6/504825 [patent_app_country] => US [patent_app_date] => 1983-06-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4009 [patent_no_of_claims] => 5 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 195 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/571/04571700.pdf [firstpage_image] =>[orig_patent_app_number] => 504825 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/504825
Page indexing system for accessing sequentially stored data representing a multi-page document Jun 15, 1983 Issued
Array ( [id] => 2223286 [patent_doc_number] => 04621339 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-11-04 [patent_title] => 'SIMD machine using cube connected cycles network architecture for vector processing' [patent_app_type] => 1 [patent_app_number] => 6/503654 [patent_app_country] => US [patent_app_date] => 1983-06-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 14 [patent_no_of_words] => 16055 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 229 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/621/04621339.pdf [firstpage_image] =>[orig_patent_app_number] => 503654 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/503654
SIMD machine using cube connected cycles network architecture for vector processing Jun 12, 1983 Issued
06/500379 DATA PROCESSING SYSTEM WITH LOGICAL PROCESSOR FACILITY Jun 1, 1983 Abandoned
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