Search

Archie E. Williams Jr.

Examiner (ID: 11265)

Most Active Art Unit
2302
Art Unit(s)
2302, 2307
Total Applications
295
Issued Applications
236
Pending Applications
0
Abandoned Applications
59

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 2147476 [patent_doc_number] => 04553223 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-11-12 [patent_title] => 'Static disturbance signal recording system having detachable programming terminal & programmable fixed part with selectively powered buffer memory' [patent_app_type] => 1 [patent_app_number] => 6/395313 [patent_app_country] => US [patent_app_date] => 1982-07-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 3 [patent_figures_cnt] => 6 [patent_no_of_words] => 4642 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 38 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/553/04553223.pdf [firstpage_image] =>[orig_patent_app_number] => 395313 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/395313
Static disturbance signal recording system having detachable programming terminal & programmable fixed part with selectively powered buffer memory Jul 5, 1982 Issued
06/393836 SPELLING VERIFICATION METHOD FOR A TYPEWRITER AND TYPEWRITER EMBODYING SAID METHOD Jun 29, 1982 Abandoned
Array ( [id] => 2225427 [patent_doc_number] => 04578751 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-03-25 [patent_title] => 'System for simultaneously programming a number of EPROMs' [patent_app_type] => 1 [patent_app_number] => 6/392053 [patent_app_country] => US [patent_app_date] => 1982-06-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 4 [patent_no_of_words] => 2591 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 250 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/578/04578751.pdf [firstpage_image] =>[orig_patent_app_number] => 392053 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/392053
System for simultaneously programming a number of EPROMs Jun 24, 1982 Issued
Array ( [id] => 2202967 [patent_doc_number] => 04495574 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-22 [patent_title] => 'Bidirectional multi-mode data transfer bus system' [patent_app_type] => 1 [patent_app_number] => 6/391705 [patent_app_country] => US [patent_app_date] => 1982-06-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 5 [patent_no_of_words] => 4004 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 364 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/495/04495574.pdf [firstpage_image] =>[orig_patent_app_number] => 391705 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/391705
Bidirectional multi-mode data transfer bus system Jun 23, 1982 Issued
Array ( [id] => 2145455 [patent_doc_number] => 04523271 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-06-11 [patent_title] => 'Software protection method and apparatus' [patent_app_type] => 1 [patent_app_number] => 6/390885 [patent_app_country] => US [patent_app_date] => 1982-06-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 1 [patent_figures_cnt] => 2 [patent_no_of_words] => 3258 [patent_no_of_claims] => 14 [patent_no_of_ind_claims] => 9 [patent_words_short_claim] => 19 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/523/04523271.pdf [firstpage_image] =>[orig_patent_app_number] => 390885 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/390885
Software protection method and apparatus Jun 21, 1982 Issued
06/378793 SYSTEM FOR TRANSMITTING COMPUTER-GENERATED DATA TO A REMOTE LOCATION May 16, 1982 Abandoned
Array ( [id] => 2173191 [patent_doc_number] => 04541076 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-09-10 [patent_title] => 'Dual port CMOS random access memory' [patent_app_type] => 1 [patent_app_number] => 6/377847 [patent_app_country] => US [patent_app_date] => 1982-05-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 12 [patent_no_of_words] => 5208 [patent_no_of_claims] => 1 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 279 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/541/04541076.pdf [firstpage_image] =>[orig_patent_app_number] => 377847 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/377847
Dual port CMOS random access memory May 12, 1982 Issued
Array ( [id] => 2187942 [patent_doc_number] => 04504902 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-03-12 [patent_title] => 'Cache arrangement for direct memory access block transfer' [patent_app_type] => 1 [patent_app_number] => 6/361499 [patent_app_country] => US [patent_app_date] => 1982-03-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 3 [patent_no_of_words] => 3555 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 102 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/504/04504902.pdf [firstpage_image] =>[orig_patent_app_number] => 361499 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/361499
Cache arrangement for direct memory access block transfer Mar 24, 1982 Issued
Array ( [id] => 2182972 [patent_doc_number] => 04530055 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-16 [patent_title] => 'Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory' [patent_app_type] => 1 [patent_app_number] => 6/354559 [patent_app_country] => US [patent_app_date] => 1982-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 23864 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 201 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/530/04530055.pdf [firstpage_image] =>[orig_patent_app_number] => 354559 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/354559
Hierarchical memory system with variable regulation and priority of writeback from cache memory to bulk memory Mar 2, 1982 Issued
Array ( [id] => 2556516 [patent_doc_number] => 04811203 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1989-03-07 [patent_title] => 'Hierarchial memory system with separate criteria for replacement and writeback without replacement' [patent_app_type] => 1 [patent_app_number] => 6/354558 [patent_app_country] => US [patent_app_date] => 1982-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 23294 [patent_no_of_claims] => 10 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/811/04811203.pdf [firstpage_image] =>[orig_patent_app_number] => 354558 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/354558
Hierarchial memory system with separate criteria for replacement and writeback without replacement Mar 2, 1982 Issued
Array ( [id] => 2182960 [patent_doc_number] => 04530054 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-07-16 [patent_title] => 'Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory' [patent_app_type] => 1 [patent_app_number] => 6/354556 [patent_app_country] => US [patent_app_date] => 1982-03-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 14 [patent_figures_cnt] => 41 [patent_no_of_words] => 23324 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 238 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/530/04530054.pdf [firstpage_image] =>[orig_patent_app_number] => 354556 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/354556
Processor-addressable timestamp for indicating oldest written-to cache entry not copied back to bulk memory Mar 2, 1982 Issued
Array ( [id] => 2137745 [patent_doc_number] => 04491910 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-01-01 [patent_title] => 'Microcomputer having data shift within memory' [patent_app_type] => 1 [patent_app_number] => 6/350951 [patent_app_country] => US [patent_app_date] => 1982-02-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 22354 [patent_no_of_claims] => 9 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 167 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/491/04491910.pdf [firstpage_image] =>[orig_patent_app_number] => 350951 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/350951
Microcomputer having data shift within memory Feb 21, 1982 Issued
06/350159 DISTRIBUTED DATA PROCESSING SYSTEM Feb 18, 1982 Abandoned
Array ( [id] => 2110943 [patent_doc_number] => 04472790 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-09-18 [patent_title] => 'Storage fetch protect override controls' [patent_app_type] => 1 [patent_app_number] => 6/345961 [patent_app_country] => US [patent_app_date] => 1982-02-05 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 2543 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 240 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/472/04472790.pdf [firstpage_image] =>[orig_patent_app_number] => 345961 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/345961
Storage fetch protect override controls Feb 4, 1982 Issued
Array ( [id] => 2205652 [patent_doc_number] => 04534011 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1985-08-06 [patent_title] => 'Peripheral attachment interface for I/O controller having cycle steal and off-line modes' [patent_app_type] => 1 [patent_app_number] => 6/345129 [patent_app_country] => US [patent_app_date] => 1982-02-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 22 [patent_no_of_words] => 6481 [patent_no_of_claims] => 7 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 216 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/534/04534011.pdf [firstpage_image] =>[orig_patent_app_number] => 345129 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/345129
Peripheral attachment interface for I/O controller having cycle steal and off-line modes Feb 1, 1982 Issued
Array ( [id] => 2096443 [patent_doc_number] => 04486855 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-04 [patent_title] => 'Activity detector usable with a serial data link' [patent_app_type] => 1 [patent_app_number] => 6/343140 [patent_app_country] => US [patent_app_date] => 1982-01-28 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 7 [patent_no_of_words] => 2482 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 363 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/486/04486855.pdf [firstpage_image] =>[orig_patent_app_number] => 343140 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/343140
Activity detector usable with a serial data link Jan 27, 1982 Issued
Array ( [id] => 2022802 [patent_doc_number] => 04419739 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1983-12-06 [patent_title] => 'Decentralized generation of synchronized clock control signals having dynamically selectable periods' [patent_app_type] => 1 [patent_app_number] => 6/342541 [patent_app_country] => US [patent_app_date] => 1982-01-25 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 7 [patent_no_of_words] => 4295 [patent_no_of_claims] => 6 [patent_no_of_ind_claims] => 1 [patent_words_short_claim] => 207 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/419/04419739.pdf [firstpage_image] =>[orig_patent_app_number] => 342541 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/342541
Decentralized generation of synchronized clock control signals having dynamically selectable periods Jan 24, 1982 Issued
Array ( [id] => 2069717 [patent_doc_number] => 04488218 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-12-11 [patent_title] => 'Dynamic priority queue occupancy scheme for access to a demand-shared bus' [patent_app_type] => 1 [patent_app_number] => 6/337674 [patent_app_country] => US [patent_app_date] => 1982-01-07 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 6279 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 6 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/488/04488218.pdf [firstpage_image] =>[orig_patent_app_number] => 337674 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/337674
Dynamic priority queue occupancy scheme for access to a demand-shared bus Jan 6, 1982 Issued
Array ( [id] => 2241387 [patent_doc_number] => 04597057 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1986-06-24 [patent_title] => 'System for compressed storage of 8-bit ASCII bytes using coded strings of 4 bit nibbles' [patent_app_type] => 1 [patent_app_number] => 6/336413 [patent_app_country] => US [patent_app_date] => 1981-12-31 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 11 [patent_figures_cnt] => 19 [patent_no_of_words] => 7662 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 8 [patent_words_short_claim] => 145 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/597/04597057.pdf [firstpage_image] =>[orig_patent_app_number] => 336413 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/336413
System for compressed storage of 8-bit ASCII bytes using coded strings of 4 bit nibbles Dec 30, 1981 Issued
Array ( [id] => 2108473 [patent_doc_number] => 04484267 [patent_country] => US [patent_kind] => NA [patent_issue_date] => 1984-11-20 [patent_title] => 'Cache sharing control in a multiprocessor' [patent_app_type] => 1 [patent_app_number] => 6/335971 [patent_app_country] => US [patent_app_date] => 1981-12-30 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 12 [patent_no_of_words] => 6918 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 60 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] => patents/04/484/04484267.pdf [firstpage_image] =>[orig_patent_app_number] => 335971 [rel_patent_id] =>[rel_patent_doc_number] =>)
06/335971
Cache sharing control in a multiprocessor Dec 29, 1981 Issued
Menu