
Arezoo Sherkat
Examiner (ID: 12013)
| Most Active Art Unit | 2434 |
| Art Unit(s) | 2494, IPBS, 2431, 2131, 2434 |
| Total Applications | 370 |
| Issued Applications | 274 |
| Pending Applications | 15 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 19905573
[patent_doc_number] => 12282579
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2025-04-22
[patent_title] => Performing actions on personal data stored in multiple databases
[patent_app_type] => utility
[patent_app_number] => 17/096326
[patent_app_country] => US
[patent_app_date] => 2020-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 11
[patent_no_of_words] => 4476
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 211
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096326
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/096326 | Performing actions on personal data stored in multiple databases | Nov 11, 2020 | Issued |
Array
(
[id] => 17276809
[patent_doc_number] => 20210383007
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-12-09
[patent_title] => DATA DELETION AND OBFUSCATION SYSTEM
[patent_app_type] => utility
[patent_app_number] => 17/096609
[patent_app_country] => US
[patent_app_date] => 2020-11-12
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 9975
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 81
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17096609
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/096609 | Data deletion and obfuscation system | Nov 11, 2020 | Issued |
Array
(
[id] => 17424103
[patent_doc_number] => 11257564
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2022-02-22
[patent_title] => Defect detection for a memory device
[patent_app_type] => utility
[patent_app_number] => 17/089180
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 8
[patent_no_of_words] => 17383
[patent_no_of_claims] => 24
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 154
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089180
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089180 | Defect detection for a memory device | Nov 3, 2020 | Issued |
Array
(
[id] => 17581481
[patent_doc_number] => 20220138336
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => VIRTUALIZING SECURE STORAGE OF A BASEBOARD MANAGEMENT CONTROLLER TO A HOST COMPUTING DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/089201
[patent_app_country] => US
[patent_app_date] => 2020-11-04
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5382
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 83
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17089201
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/089201 | Virtualizing secure storage of a baseboard management controller to a host computing device | Nov 3, 2020 | Issued |
Array
(
[id] => 17438733
[patent_doc_number] => 11264073
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-03-01
[patent_title] => Device and method for performing matrix operation
[patent_app_type] => utility
[patent_app_number] => 17/085361
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 8
[patent_figures_cnt] => 9
[patent_no_of_words] => 4516
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085361
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/085361 | Device and method for performing matrix operation | Oct 29, 2020 | Issued |
Array
(
[id] => 17582575
[patent_doc_number] => 20220139430
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-05-05
[patent_title] => MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/085398
[patent_app_country] => US
[patent_app_date] => 2020-10-30
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7670
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 134
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17085398
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/085398 | Memory device | Oct 29, 2020 | Issued |
Array
(
[id] => 17566297
[patent_doc_number] => 20220130446
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2022-04-28
[patent_title] => SUB-WORD LINE DRIVER PLACEMENT FOR MEMORY DEVICE
[patent_app_type] => utility
[patent_app_number] => 17/081799
[patent_app_country] => US
[patent_app_date] => 2020-10-27
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5645
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 173
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17081799
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/081799 | Sub-word line driver placement for memory device | Oct 26, 2020 | Issued |
Array
(
[id] => 19377569
[patent_doc_number] => 12069160
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2024-08-20
[patent_title] => Electronic control unit, apparatus for performing control operations on an electronic control unit, and corresponding methods and computer programs
[patent_app_type] => utility
[patent_app_number] => 17/799564
[patent_app_country] => US
[patent_app_date] => 2020-10-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 3
[patent_figures_cnt] => 5
[patent_no_of_words] => 8270
[patent_no_of_claims] => 19
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 87
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17799564
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/799564 | Electronic control unit, apparatus for performing control operations on an electronic control unit, and corresponding methods and computer programs | Oct 21, 2020 | Issued |
Array
(
[id] => 18331643
[patent_doc_number] => 11636893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2023-04-25
[patent_title] => Memory device with multiple row buffers
[patent_app_type] => utility
[patent_app_number] => 17/073621
[patent_app_country] => US
[patent_app_date] => 2020-10-19
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 13
[patent_no_of_words] => 8163
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 108
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17073621
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/073621 | Memory device with multiple row buffers | Oct 18, 2020 | Issued |
Array
(
[id] => 17409997
[patent_doc_number] => 11250893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 17/071107
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16511
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071107 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Oct 14, 2020 | Issued |
Array
(
[id] => 17409997
[patent_doc_number] => 11250893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 17/071107
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16511
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071107 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Oct 14, 2020 | Issued |
Array
(
[id] => 17409997
[patent_doc_number] => 11250893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 17/071107
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16511
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071107 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Oct 14, 2020 | Issued |
Array
(
[id] => 17409997
[patent_doc_number] => 11250893
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2022-02-15
[patent_title] => Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle
[patent_app_type] => utility
[patent_app_number] => 17/071107
[patent_app_country] => US
[patent_app_date] => 2020-10-15
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 15
[patent_no_of_words] => 16511
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 101
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17071107
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/071107 | Apparatuses and methods for setting a duty cycle adjuster for improving clock duty cycle | Oct 14, 2020 | Issued |
Array
(
[id] => 16600406
[patent_doc_number] => 20210026937
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-01-28
[patent_title] => SESSION BASED ELASTIC LAYERING
[patent_app_type] => utility
[patent_app_number] => 17/066757
[patent_app_country] => US
[patent_app_date] => 2020-10-09
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 5159
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -15
[patent_words_short_claim] => 164
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17066757
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/066757 | SESSION BASED ELASTIC LAYERING | Oct 8, 2020 | Abandoned |
Array
(
[id] => 17310003
[patent_doc_number] => 11211128
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2021-12-28
[patent_title] => Performing threshold voltage offset bin selection by package for memory devices
[patent_app_type] => utility
[patent_app_number] => 17/061713
[patent_app_country] => US
[patent_app_date] => 2020-10-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 11
[patent_no_of_words] => 10959
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17061713
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/061713 | Performing threshold voltage offset bin selection by package for memory devices | Oct 1, 2020 | Issued |
Array
(
[id] => 18790336
[patent_doc_number] => 20230379150
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2023-11-23
[patent_title] => METHODS AND APPARATUSES FOR PROVIDING COMMUNICATION BETWEEN A SERVER AND A CLIENT DEVICE VIA A PROXY NODE
[patent_app_type] => utility
[patent_app_number] => 18/029069
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 7217
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 18029069
[rel_patent_id] =>[rel_patent_doc_number] =>) 18/029069 | METHODS AND APPARATUSES FOR PROVIDING COMMUNICATION BETWEEN A SERVER AND A CLIENT DEVICE VIA A PROXY NODE | Sep 28, 2020 | Pending |
Array
(
[id] => 16943946
[patent_doc_number] => 11056194
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-07-06
[patent_title] => Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same
[patent_app_type] => utility
[patent_app_number] => 17/036387
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 16
[patent_figures_cnt] => 18
[patent_no_of_words] => 12883
[patent_no_of_claims] => 10
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 192
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17036387
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/036387 | Method of erasing data in nonvolatile memory device, nonvolatile memory device performing the same and memory system including the same | Sep 28, 2020 | Issued |
Array
(
[id] => 16781413
[patent_doc_number] => 20210118492
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2021-04-22
[patent_title] => TWO-STAGE SIGNALING FOR VOLTAGE DRIVER COORDINATION IN INTEGRATED CIRCUIT MEMORY DEVICES
[patent_app_type] => utility
[patent_app_number] => 17/037497
[patent_app_country] => US
[patent_app_date] => 2020-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 6501
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -17
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17037497
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/037497 | Two-stage signaling for voltage driver coordination in integrated circuit memory devices | Sep 28, 2020 | Issued |
Array
(
[id] => 19101850
[patent_doc_number] => 20240121078
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2024-04-11
[patent_title] => METHOD FOR CONTROLLING VALIDITY OF AN ATTRIBUTE
[patent_app_type] => utility
[patent_app_number] => 17/768239
[patent_app_country] => US
[patent_app_date] => 2020-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 4762
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -11
[patent_words_short_claim] => 152
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17768239
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/768239 | Method for controlling validity of an attribute | Sep 27, 2020 | Issued |
Array
(
[id] => 16788975
[patent_doc_number] => 10991412
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2021-04-27
[patent_title] => Storage device and method for operating storage device
[patent_app_type] => utility
[patent_app_number] => 17/030766
[patent_app_country] => US
[patent_app_date] => 2020-09-24
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 21
[patent_no_of_words] => 7549
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 100
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17030766
[rel_patent_id] =>[rel_patent_doc_number] =>) 17/030766 | Storage device and method for operating storage device | Sep 23, 2020 | Issued |