Search

Arezoo Sherkat

Examiner (ID: 12013)

Most Active Art Unit
2434
Art Unit(s)
2494, IPBS, 2431, 2131, 2434
Total Applications
370
Issued Applications
274
Pending Applications
15
Abandoned Applications
81

Applications

Application numberTitle of the applicationFiling DateStatus
Array ( [id] => 17826760 [patent_doc_number] => 11431722 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-08-30 [patent_title] => Segregation of protected resources from network frontend [patent_app_type] => utility [patent_app_number] => 16/793433 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 2 [patent_figures_cnt] => 2 [patent_no_of_words] => 4166 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 264 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793433 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793433
Segregation of protected resources from network frontend Feb 17, 2020 Issued
Array ( [id] => 16788266 [patent_doc_number] => 10990700 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-04-27 [patent_title] => Internet profile dilution device (IPDD) [patent_app_type] => utility [patent_app_number] => 16/793806 [patent_app_country] => US [patent_app_date] => 2020-02-18 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 3452 [patent_no_of_claims] => 11 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 319 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16793806 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/793806
Internet profile dilution device (IPDD) Feb 17, 2020 Issued
Array ( [id] => 19680469 [patent_doc_number] => 12192348 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2025-01-07 [patent_title] => Key management in an integrated circuit [patent_app_type] => utility [patent_app_number] => 17/432153 [patent_app_country] => US [patent_app_date] => 2020-02-14 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 4 [patent_no_of_words] => 6612 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 89 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17432153 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/432153
Key management in an integrated circuit Feb 13, 2020 Issued
Array ( [id] => 16566632 [patent_doc_number] => 10892006 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-01-12 [patent_title] => Write leveling for a memory device [patent_app_type] => utility [patent_app_number] => 16/786661 [patent_app_country] => US [patent_app_date] => 2020-02-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 6 [patent_no_of_words] => 5002 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 80 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16786661 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/786661
Write leveling for a memory device Feb 9, 2020 Issued
Array ( [id] => 17279043 [patent_doc_number] => 20210385241 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-12-09 [patent_title] => DETECTION DEVICE AND DETECTION METHOD [patent_app_type] => utility [patent_app_number] => 17/431863 [patent_app_country] => US [patent_app_date] => 2020-02-04 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 42 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17431863 [rel_patent_id] =>[rel_patent_doc_number] =>)
17/431863
Detection device and detection method Feb 3, 2020 Issued
Array ( [id] => 16759564 [patent_doc_number] => 10978119 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-04-13 [patent_title] => Memory device and method of operating the same [patent_app_type] => utility [patent_app_number] => 16/773643 [patent_app_country] => US [patent_app_date] => 2020-01-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 16 [patent_no_of_words] => 6951 [patent_no_of_claims] => 33 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 59 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16773643 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/773643
Memory device and method of operating the same Jan 26, 2020 Issued
Array ( [id] => 17197112 [patent_doc_number] => 11165890 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-11-02 [patent_title] => Secure client-server communication [patent_app_type] => utility [patent_app_number] => 16/750915 [patent_app_country] => US [patent_app_date] => 2020-01-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 8912 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 232 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16750915 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/750915
Secure client-server communication Jan 22, 2020 Issued
Array ( [id] => 16637779 [patent_doc_number] => 10916293 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit [patent_app_type] => utility [patent_app_number] => 16/747553 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 5 [patent_figures_cnt] => 5 [patent_no_of_words] => 5741 [patent_no_of_claims] => 13 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 190 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747553 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747553
Target row refresh mechanism capable of effectively determining target row address to effectively mitigate row hammer errors without using counter circuit Jan 20, 2020 Issued
Array ( [id] => 17926796 [patent_doc_number] => 11470069 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-10-11 [patent_title] => Web browser-based device communication workflow [patent_app_type] => utility [patent_app_number] => 16/747797 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 6 [patent_no_of_words] => 7336 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 178 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747797 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747797
Web browser-based device communication workflow Jan 20, 2020 Issued
Array ( [id] => 16668236 [patent_doc_number] => 10937489 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-03-02 [patent_title] => Pre-charge circuit of SRAM controller and pre charging method thereof [patent_app_type] => utility [patent_app_number] => 16/747559 [patent_app_country] => US [patent_app_date] => 2020-01-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 15 [patent_no_of_words] => 4843 [patent_no_of_claims] => 12 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16747559 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/747559
Pre-charge circuit of SRAM controller and pre charging method thereof Jan 20, 2020 Issued
Array ( [id] => 16699690 [patent_doc_number] => 10950298 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-03-16 [patent_title] => Mixed threshold voltage memory array [patent_app_type] => utility [patent_app_number] => 16/745749 [patent_app_country] => US [patent_app_date] => 2020-01-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 9 [patent_figures_cnt] => 9 [patent_no_of_words] => 5203 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16745749 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/745749
Mixed threshold voltage memory array Jan 16, 2020 Issued
Array ( [id] => 15906249 [patent_doc_number] => 20200152645 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-14 [patent_title] => Memory Cell And An Array Of Memory Cells [patent_app_type] => utility [patent_app_number] => 16/743088 [patent_app_country] => US [patent_app_date] => 2020-01-15 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4131 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -6 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16743088 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/743088
Memory cell and an array of memory cells Jan 14, 2020 Issued
Array ( [id] => 16834970 [patent_doc_number] => 11011228 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-05-18 [patent_title] => Memory device having an increased sensing margin [patent_app_type] => utility [patent_app_number] => 16/741153 [patent_app_country] => US [patent_app_date] => 2020-01-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 26 [patent_figures_cnt] => 28 [patent_no_of_words] => 13150 [patent_no_of_claims] => 17 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 153 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16741153 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/741153
Memory device having an increased sensing margin Jan 12, 2020 Issued
Array ( [id] => 15966663 [patent_doc_number] => 20200167083 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY [patent_app_type] => utility [patent_app_number] => 16/739294 [patent_app_country] => US [patent_app_date] => 2020-01-10 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 4508 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16739294 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/739294
TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY Jan 9, 2020 Abandoned
Array ( [id] => 17396676 [patent_doc_number] => 11245704 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2022-02-08 [patent_title] => Automatically executing responsive actions based on a verification of an account lineage chain [patent_app_type] => utility [patent_app_number] => 16/737502 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 24 [patent_figures_cnt] => 24 [patent_no_of_words] => 17117 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 184 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737502 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737502
Automatically executing responsive actions based on a verification of an account lineage chain Jan 7, 2020 Issued
Array ( [id] => 16943963 [patent_doc_number] => 11056211 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-07-06 [patent_title] => Apparatus and method for handling temperature dependent failures in a memory device [patent_app_type] => utility [patent_app_number] => 16/737551 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 6 [patent_figures_cnt] => 8 [patent_no_of_words] => 5469 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 165 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737551 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737551
Apparatus and method for handling temperature dependent failures in a memory device Jan 7, 2020 Issued
Array ( [id] => 16951434 [patent_doc_number] => 20210210126 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2021-07-08 [patent_title] => TIMING CHAINS FOR ACCESSING MEMORY CELLS [patent_app_type] => utility [patent_app_number] => 16/737139 [patent_app_country] => US [patent_app_date] => 2020-01-08 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12377 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -21 [patent_words_short_claim] => 107 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16737139 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/737139
Timing chains for accessing memory cells Jan 7, 2020 Issued
Array ( [id] => 16637761 [patent_doc_number] => 10916275 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2021-02-09 [patent_title] => Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories [patent_app_type] => utility [patent_app_number] => 16/735539 [patent_app_country] => US [patent_app_date] => 2020-01-06 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 12 [patent_no_of_words] => 10067 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 66 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16735539 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/735539
Write driver and pre-charge circuitry for high performance pseudo-dual port (PDP) memories Jan 5, 2020 Issued
Array ( [id] => 16609050 [patent_doc_number] => 10910063 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2021-02-02 [patent_title] => Memory device and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/732949 [patent_app_country] => US [patent_app_date] => 2020-01-02 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 21 [patent_no_of_words] => 16440 [patent_no_of_claims] => 21 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 112 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16732949 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/732949
Memory device and operating method thereof Jan 1, 2020 Issued
Array ( [id] => 16536247 [patent_doc_number] => 10878860 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2020-12-29 [patent_title] => Multi-level signaling scheme for memory interface [patent_app_type] => utility [patent_app_number] => 16/728451 [patent_app_country] => US [patent_app_date] => 2019-12-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 7 [patent_figures_cnt] => 9 [patent_no_of_words] => 6691 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 85 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16728451 [rel_patent_id] =>[rel_patent_doc_number] =>)
16/728451
Multi-level signaling scheme for memory interface Dec 26, 2019 Issued
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