Arezoo Sherkat

Array ( [id] => 15314997 [patent_doc_number] => 10522208 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-31 [patent_title] => Apparatuses and methods for drivers with reduced noise [patent_app_type] => utility [patent_app_number] => 16/144693 [patent_app_country] => US [patent_app_date] => 2018-09-27 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 12 [patent_figures_cnt] => 13 [patent_no_of_words] => 8627 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 156 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16144693 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14784351 [patent_doc_number] => 20190267073 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR MEMORY DEVICE AND METHOD FOR OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/139573 [patent_app_country] => US [patent_app_date] => 2018-09-24 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12564 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 47 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16139573 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15400731 [patent_doc_number] => 10541025 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-01-21 [patent_title] => Switching block configuration bit comprising a non-volatile memory cell [patent_app_type] => utility [patent_app_number] => 16/138673 [patent_app_country] => US [patent_app_date] => 2018-09-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 10 [patent_figures_cnt] => 11 [patent_no_of_words] => 15849 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 259 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16138673 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16067171 [patent_doc_number] => 10692544 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-06-23 [patent_title] => Methods of command based and current limit controlled memory device power up [patent_app_type] => utility [patent_app_number] => 16/137133 [patent_app_country] => US [patent_app_date] => 2018-09-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 9 [patent_no_of_words] => 4703 [patent_no_of_claims] => 19 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 57 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16137133 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14784305 [patent_doc_number] => 20190267050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-29 [patent_title] => SEMICONDUCTOR DEVICES [patent_app_type] => utility [patent_app_number] => 16/110489 [patent_app_country] => US [patent_app_date] => 2018-08-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7727 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 95 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16110489 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15563899 [patent_doc_number] => 20200066361 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-02-27 [patent_title] => METHODS FOR READ THRESHOLD VOLTAGE SHIFTING IN NON-VOLATILE MEMORY [patent_app_type] => utility [patent_app_number] => 16/109689 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9033 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => 0 [patent_words_short_claim] => 2 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109689 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14721887 [patent_doc_number] => 20190252007 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-15 [patent_title] => MEMORY SYSTEM AND OPERATING METHOD OF THE SAME [patent_app_type] => utility [patent_app_number] => 16/109169 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11293 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -16 [patent_words_short_claim] => 51 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16109169 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16372173 [patent_doc_number] => 10803939 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-10-13 [patent_title] => Techniques for programming a memory cell [patent_app_type] => utility [patent_app_number] => 16/108784 [patent_app_country] => US [patent_app_date] => 2018-08-22 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 8 [patent_figures_cnt] => 8 [patent_no_of_words] => 14350 [patent_no_of_claims] => 18 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 94 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16108784 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13595003 [patent_doc_number] => 20180349050 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-12-06 [patent_title] => SRAM-BASED AUTHENTICATION CIRCUIT [patent_app_type] => utility [patent_app_number] => 16/100008 [patent_app_country] => US [patent_app_date] => 2018-08-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7036 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16100008 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 14658263 [patent_doc_number] => 20190236260 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-08-01 [patent_title] => ELECTRONIC APPARATUS, CONTROL SYSTEM, CONTROL METHOD, AND STORAGE MEDIUM [patent_app_type] => utility [patent_app_number] => 16/042545 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 12046 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -14 [patent_words_short_claim] => 96 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16042545 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15215427 [patent_doc_number] => 20190370400 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-12-05 [patent_title] => ELECTRONIC EVIDENCE TRANSFER [patent_app_type] => utility [patent_app_number] => 16/042209 [patent_app_country] => US [patent_app_date] => 2018-07-23 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 5943 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -20 [patent_words_short_claim] => 142 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16042209 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15971343 [patent_doc_number] => 20200169423 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2020-05-28 [patent_title] => PUF WITH DISSOLVABLE CONDUCTIVE PATHS [patent_app_type] => utility [patent_app_number] => 16/493263 [patent_app_country] => US [patent_app_date] => 2018-07-20 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 9067 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 169 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16493263 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 16308756 [patent_doc_number] => 10777566 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2020-09-15 [patent_title] => 3D array arranged for memory and in-memory sum-of-products operations [patent_app_type] => utility [patent_app_number] => 16/037281 [patent_app_country] => US [patent_app_date] => 2018-07-17 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 28 [patent_figures_cnt] => 28 [patent_no_of_words] => 12706 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 4 [patent_words_short_claim] => 110 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16037281 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13878251 [patent_doc_number] => 20190035466 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2019-01-31 [patent_title] => MEMORY DEVICE INCLUDING NAND STRINGS AND METHOD OF OPERATING THE SAME [patent_app_type] => utility [patent_app_number] => 16/035958 [patent_app_country] => US [patent_app_date] => 2018-07-16 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 11554 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -17 [patent_words_short_claim] => 76 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035958 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15060965 [patent_doc_number] => 10460794 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-10-29 [patent_title] => SRAM array [patent_app_type] => utility [patent_app_number] => 16/035006 [patent_app_country] => US [patent_app_date] => 2018-07-13 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 20 [patent_figures_cnt] => 20 [patent_no_of_words] => 11004 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 274 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16035006 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 17565425 [patent_doc_number] => 20220129574 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2022-04-28 [patent_title] => METHOD FOR SETTING UP A SECURE HIERARCHICAL REFERENCING SYSTEM [patent_app_type] => utility [patent_app_number] => 17/257684 [patent_app_country] => US [patent_app_date] => 2018-07-12 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 2656 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -4 [patent_words_short_claim] => 596 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 17257684 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13558451 [patent_doc_number] => 20180330773 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => Methods of Reading and Writing Data in a Thyristor Random Access Memory [patent_app_type] => utility [patent_app_number] => 16/030819 [patent_app_country] => US [patent_app_date] => 2018-07-09 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 6653 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -8 [patent_words_short_claim] => 149 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16030819 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 13556943 [patent_doc_number] => 20180330019 [patent_country] => US [patent_kind] => A1 [patent_issue_date] => 2018-11-15 [patent_title] => DATA DRIVEN SHRINKAGE COMPENSATION [patent_app_type] => utility [patent_app_number] => 16/026554 [patent_app_country] => US [patent_app_date] => 2018-07-03 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 0 [patent_figures_cnt] => 0 [patent_no_of_words] => 7012 [patent_no_of_claims] => 0 [patent_no_of_ind_claims] => -18 [patent_words_short_claim] => 121 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => publication [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16026554 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15233705 [patent_doc_number] => 10504581 [patent_country] => US [patent_kind] => B1 [patent_issue_date] => 2019-12-10 [patent_title] => Memory apparatus and operating method thereof [patent_app_type] => utility [patent_app_number] => 16/018060 [patent_app_country] => US [patent_app_date] => 2018-06-26 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 4 [patent_figures_cnt] => 6 [patent_no_of_words] => 2507 [patent_no_of_claims] => 8 [patent_no_of_ind_claims] => 2 [patent_words_short_claim] => 106 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16018060 [rel_patent_id] =>[rel_patent_doc_number] =>)

Array ( [id] => 15138983 [patent_doc_number] => 10482973 [patent_country] => US [patent_kind] => B2 [patent_issue_date] => 2019-11-19 [patent_title] => Memory devices including a word line defect detection circuit [patent_app_type] => utility [patent_app_number] => 16/014222 [patent_app_country] => US [patent_app_date] => 2018-06-21 [patent_effective_date] => 0000-00-00 [patent_drawing_sheets_cnt] => 19 [patent_figures_cnt] => 19 [patent_no_of_words] => 10327 [patent_no_of_claims] => 20 [patent_no_of_ind_claims] => 3 [patent_words_short_claim] => 111 [patent_maintenance] => 1 [patent_no_of_assignments] => 0 [patent_current_assignee] =>[type] => patent [pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 16014222 [rel_patent_id] =>[rel_patent_doc_number] =>)