
Arezoo Sherkat
Examiner (ID: 12013)
| Most Active Art Unit | 2434 |
| Art Unit(s) | 2494, IPBS, 2431, 2131, 2434 |
| Total Applications | 370 |
| Issued Applications | 274 |
| Pending Applications | 15 |
| Abandoned Applications | 81 |
Applications
| Application number | Title of the application | Filing Date | Status |
|---|---|---|---|
Array
(
[id] => 13722285
[patent_doc_number] => 20170372097
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-12-28
[patent_title] => COMPUTER-IMPLEMENTED METHOD FOR IMPROVING A SOCIAL NETWORK SITE COMPUTER NETWORK, AND TERMINAL, SYSTEM AND COMPUTER READABLE MEDIUM FOR THE SAME
[patent_app_type] => utility
[patent_app_number] => 15/540261
[patent_app_country] => US
[patent_app_date] => 2015-12-16
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 0
[patent_figures_cnt] => 0
[patent_no_of_words] => 14214
[patent_no_of_claims] => 0
[patent_no_of_ind_claims] => -19
[patent_words_short_claim] => 2
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15540261
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/540261 | Computer-implemented method for improving a social network site computer network, and terminal, system and computer readable medium for the same | Dec 15, 2015 | Issued |
Array
(
[id] => 10752899
[patent_doc_number] => 20160099051
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-04-07
[patent_title] => 'RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/967457
[patent_app_country] => US
[patent_app_date] => 2015-12-14
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 14
[patent_figures_cnt] => 14
[patent_no_of_words] => 4754
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14967457
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/967457 | RESISTANCE CHANGE MEMORY AND FORMING METHOD OF THE RESISTANCE CHANGE DEVICE | Dec 13, 2015 | Abandoned |
Array
(
[id] => 11079061
[patent_doc_number] => 20160276026
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-09-22
[patent_title] => 'SEMICONDUCTOR STORAGE DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/962777
[patent_app_country] => US
[patent_app_date] => 2015-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 8912
[patent_no_of_claims] => 12
[patent_no_of_ind_claims] => 1
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14962777
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/962777 | Semiconductor storage device | Dec 7, 2015 | Issued |
Array
(
[id] => 11466570
[patent_doc_number] => 09583209
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-02-28
[patent_title] => 'High density memory architecture'
[patent_app_type] => utility
[patent_app_number] => 14/963111
[patent_app_country] => US
[patent_app_date] => 2015-12-08
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 7
[patent_no_of_words] => 6834
[patent_no_of_claims] => 15
[patent_no_of_ind_claims] => 8
[patent_words_short_claim] => 171
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14963111
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/963111 | High density memory architecture | Dec 7, 2015 | Issued |
Array
(
[id] => 11411521
[patent_doc_number] => 09558830
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2017-01-31
[patent_title] => 'Semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/961643
[patent_app_country] => US
[patent_app_date] => 2015-12-07
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 21
[patent_figures_cnt] => 25
[patent_no_of_words] => 21583
[patent_no_of_claims] => 11
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 452
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14961643
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/961643 | Semiconductor device | Dec 6, 2015 | Issued |
Array
(
[id] => 10740521
[patent_doc_number] => 20160086672
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-03-24
[patent_title] => 'ACCESS LINE MANAGEMENT IN A MEMORY DEVICE'
[patent_app_type] => utility
[patent_app_number] => 14/958217
[patent_app_country] => US
[patent_app_date] => 2015-12-03
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 5568
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14958217
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/958217 | Access line management in a memory device | Dec 2, 2015 | Issued |
Array
(
[id] => 11585593
[patent_doc_number] => 09640242
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-05-02
[patent_title] => 'System and method for temperature compensated refresh of dynamic random access memory'
[patent_app_type] => utility
[patent_app_number] => 14/956565
[patent_app_country] => US
[patent_app_date] => 2015-12-02
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 9956
[patent_no_of_claims] => 14
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 133
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14956565
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/956565 | System and method for temperature compensated refresh of dynamic random access memory | Dec 1, 2015 | Issued |
Array
(
[id] => 10983985
[patent_doc_number] => 20160180929
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-06-23
[patent_title] => 'Variable Resistance Memory Device'
[patent_app_type] => utility
[patent_app_number] => 14/955789
[patent_app_country] => US
[patent_app_date] => 2015-12-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 17
[patent_no_of_words] => 22910
[patent_no_of_claims] => 22
[patent_no_of_ind_claims] => 5
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14955789
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/955789 | Variable resistance memory device | Nov 30, 2015 | Issued |
Array
(
[id] => 12121387
[patent_doc_number] => 20180004974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2018-01-04
[patent_title] => 'SECURE TRANSMISSION OF SENSITIVE MEASUREMENT DATA IN AN AUTOMATION NETWORK'
[patent_app_type] => utility
[patent_app_number] => 15/541612
[patent_app_country] => US
[patent_app_date] => 2015-11-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 6553
[patent_no_of_claims] => 13
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15541612
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/541612 | Secure transmission of sensitive measurement data in an automation network | Nov 25, 2015 | Issued |
Array
(
[id] => 11194072
[patent_doc_number] => 09424890
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-08-23
[patent_title] => 'Semiconductor device and driving method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/951937
[patent_app_country] => US
[patent_app_date] => 2015-11-25
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 33
[patent_figures_cnt] => 64
[patent_no_of_words] => 27516
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 172
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14951937
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/951937 | Semiconductor device and driving method thereof | Nov 24, 2015 | Issued |
Array
(
[id] => 11397759
[patent_doc_number] => 20170018295
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-01-19
[patent_title] => 'BITLINE SENSEAMPLIFIER AND SEMICONDUCTOR MEMORY APPARATUS USING THE SAME'
[patent_app_type] => utility
[patent_app_number] => 14/946959
[patent_app_country] => US
[patent_app_date] => 2015-11-20
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 10
[patent_figures_cnt] => 10
[patent_no_of_words] => 10214
[patent_no_of_claims] => 23
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14946959
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/946959 | Bitline senseamplifier and semiconductor memory apparatus using the same | Nov 19, 2015 | Issued |
Array
(
[id] => 11781571
[patent_doc_number] => 09390769
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-07-12
[patent_title] => 'Sense amplifiers and multiplexed latches'
[patent_app_type] => utility
[patent_app_number] => 14/922323
[patent_app_country] => US
[patent_app_date] => 2015-10-26
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 11
[patent_figures_cnt] => 11
[patent_no_of_words] => 4972
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 160
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14922323
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/922323 | Sense amplifiers and multiplexed latches | Oct 25, 2015 | Issued |
Array
(
[id] => 11996644
[patent_doc_number] => 20170300799
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2017-10-19
[patent_title] => 'Smartcard'
[patent_app_type] => utility
[patent_app_number] => 15/521318
[patent_app_country] => US
[patent_app_date] => 2015-10-21
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 12
[patent_figures_cnt] => 12
[patent_no_of_words] => 10242
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 2
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 15521318
[rel_patent_id] =>[rel_patent_doc_number] =>) 15/521318 | Smartcard | Oct 20, 2015 | Issued |
Array
(
[id] => 11391614
[patent_doc_number] => 09552863
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2017-01-24
[patent_title] => 'Memory device with sampled resistance controlled write voltages'
[patent_app_type] => utility
[patent_app_number] => 14/872438
[patent_app_country] => US
[patent_app_date] => 2015-10-01
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 6616
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 107
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14872438
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/872438 | Memory device with sampled resistance controlled write voltages | Sep 30, 2015 | Issued |
Array
(
[id] => 11239731
[patent_doc_number] => 09466376
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-10-11
[patent_title] => 'Semiconductor memory device and operating method thereof'
[patent_app_type] => utility
[patent_app_number] => 14/868586
[patent_app_country] => US
[patent_app_date] => 2015-09-29
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 9
[patent_no_of_words] => 9304
[patent_no_of_claims] => 16
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 105
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868586
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/868586 | Semiconductor memory device and operating method thereof | Sep 28, 2015 | Issued |
Array
(
[id] => 11227310
[patent_doc_number] => 09455036
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-27
[patent_title] => 'System architectures with data transfer paths between different memory types'
[patent_app_type] => utility
[patent_app_number] => 14/868363
[patent_app_country] => US
[patent_app_date] => 2015-09-28
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 13
[patent_figures_cnt] => 38
[patent_no_of_words] => 9977
[patent_no_of_claims] => 17
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 113
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14868363
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/868363 | System architectures with data transfer paths between different memory types | Sep 27, 2015 | Issued |
Array
(
[id] => 10665830
[patent_doc_number] => 20160011974
[patent_country] => US
[patent_kind] => A1
[patent_issue_date] => 2016-01-14
[patent_title] => 'TECHNIQUES FOR CONTROLLING RECYCLING OF BLOCKS OF MEMORY'
[patent_app_type] => utility
[patent_app_number] => 14/862195
[patent_app_country] => US
[patent_app_date] => 2015-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 6
[patent_figures_cnt] => 6
[patent_no_of_words] => 4517
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 0
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => publication
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14862195
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/862195 | Techniques for controlling recycling of blocks of memory | Sep 22, 2015 | Issued |
Array
(
[id] => 11221367
[patent_doc_number] => 09449709
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-20
[patent_title] => 'Volatile memory and one-time program (OTP) compatible memory cell and programming method'
[patent_app_type] => utility
[patent_app_number] => 14/863417
[patent_app_country] => US
[patent_app_date] => 2015-09-23
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 17
[patent_figures_cnt] => 25
[patent_no_of_words] => 9823
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 4
[patent_words_short_claim] => 88
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14863417
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/863417 | Volatile memory and one-time program (OTP) compatible memory cell and programming method | Sep 22, 2015 | Issued |
Array
(
[id] => 11227302
[patent_doc_number] => 09455028
[patent_country] => US
[patent_kind] => B1
[patent_issue_date] => 2016-09-27
[patent_title] => 'Adaptive negative bit line write assist'
[patent_app_type] => utility
[patent_app_number] => 14/860916
[patent_app_country] => US
[patent_app_date] => 2015-09-22
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 5
[patent_figures_cnt] => 5
[patent_no_of_words] => 4727
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 111
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14860916
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/860916 | Adaptive negative bit line write assist | Sep 21, 2015 | Issued |
Array
(
[id] => 10645129
[patent_doc_number] => 09362002
[patent_country] => US
[patent_kind] => B2
[patent_issue_date] => 2016-06-07
[patent_title] => 'Stacked semiconductor device'
[patent_app_type] => utility
[patent_app_number] => 14/858888
[patent_app_country] => US
[patent_app_date] => 2015-09-18
[patent_effective_date] => 0000-00-00
[patent_drawing_sheets_cnt] => 7
[patent_figures_cnt] => 8
[patent_no_of_words] => 5060
[patent_no_of_claims] => 20
[patent_no_of_ind_claims] => 3
[patent_words_short_claim] => 118
[patent_maintenance] => 1
[patent_no_of_assignments] => 0
[patent_current_assignee] =>[type] => patent
[pdf_file] =>[firstpage_image] =>[orig_patent_app_number] => 14858888
[rel_patent_id] =>[rel_patent_doc_number] =>) 14/858888 | Stacked semiconductor device | Sep 17, 2015 | Issued |